phone.map.rpt

卡式计费电话电路,用verilogHDL编写,主要完成模拟真实电话的功能

; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name         ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------------+
; |account_top               ; 257 (0)     ; 147          ; 0           ; 30   ; 0            ; 110 (0)      ; 4 (0)             ; 143 (0)          ; 119 (0)         ; |account_top                ;
;    |account2:inst2|        ; 224 (224)   ; 123          ; 0           ; 0    ; 0            ; 101 (101)    ; 3 (3)             ; 120 (120)        ; 96 (96)         ; |account_top|account2:inst2 ;
;    |clkdiv:33|             ; 33 (33)     ; 24           ; 0           ; 0    ; 0            ; 9 (9)        ; 1 (1)             ; 23 (23)          ; 23 (23)         ; |account_top|clkdiv:33      ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 147   ;
; Number of registers using Synchronous Clear  ; 124   ;
; Number of registers using Synchronous Load   ; 6     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 11    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                          ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------+
; 3:1                ; 32 bits   ; 64 LEs        ; 32 LEs               ; 32 LEs                 ; Yes        ; |account_top|account2:inst2|num1[9]       ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |account_top|account2:inst2|decide_reg[1] ;
; 3:1                ; 32 bits   ; 64 LEs        ; 32 LEs               ; 32 LEs                 ; Yes        ; |account_top|account2:inst2|num2[17]      ;
; 4:1                ; 32 bits   ; 64 LEs        ; 32 LEs               ; 32 LEs                 ; Yes        ; |account_top|account2:inst2|temp[28]      ;
; 6:1                ; 7 bits    ; 28 LEs        ; 14 LEs               ; 14 LEs                 ; Yes        ; |account_top|account2:inst2|money[1]      ;
; 8:1                ; 4 bits    ; 20 LEs        ; 4 LEs                ; 16 LEs                 ; Yes        ; |account_top|account2:inst2|dtime[0]      ;
; 9:1                ; 4 bits    ; 24 LEs        ; 4 LEs                ; 20 LEs                 ; Yes        ; |account_top|account2:inst2|dtime[4]      ;
; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |account_top|account2:inst2|money~12      ;
; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |account_top|account2:inst2|money~7       ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------+


+--------------------------------------------------------+
; Parameter Settings for User Entity Instance: clkdiv:33 ;
+----------------+---------+-----------------------------+
; Parameter Name ; Value   ; Type                        ;
+----------------+---------+-----------------------------+
; clk_count_max  ; 4999999 ; Integer                     ;
+----------------+---------+-----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/phone.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
    Info: Processing started: Mon Mar 13 22:37:31 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off phone -c phone
Info: Found 1 design units, including 1 entities, in source file account1.v
    Info: Found entity 1: account1
Info: Found 1 design units, including 1 entities, in source file clkdiv.v
    Info: Found entity 1: clkdiv
Info: Found 1 design units, including 1 entities, in source file account.v
    Info: Found entity 1: account
Info: Found 1 design units, including 1 entities, in source file account_top.bdf
    Info: Found entity 1: account_top
Info: Found 1 design units, including 1 entities, in source file abc.v
    Info: Found entity 1: abc
Warning: (10268) Verilog HDL information at account2.v(195): Always Construct contains both blocking and non-blocking assignments
Info: Found 1 design units, including 1 entities, in source file account2.v
    Info: Found entity 1: account2
Info: Found 1 design units, including 1 entities, in source file p7segment_new.v
    Info: Found entity 1: p7segment_new
Info: Elaborating entity "account_top" for the top level hierarchy
Warning: Block or symbol "p7segment_new" of instance "inst" overlaps another block or symbol
Warning: Block or symbol "p7segment_new" of instance "inst3" overlaps another block or symbol
Info: Elaborating entity "account2" for hierarchy "account2:inst2"
Info: (10035) Verilog HDL or VHDL information at account2.v(33): object "set_reg" declared but not used
Info: (10035) Verilog HDL or VHDL information at account2.v(43): object "reset_ena" declared but not used
Warning: Verilog HDL assignment warning at account2.v(49): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at account2.v(51): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at account2.v(61): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at account2.v(63): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at account2.v(64): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at account2.v(68): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at account2.v(74): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at account2.v(99): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at account2.v(100): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at account2.v(104): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at account2.v(110): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at account2.v(120): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at account2.v(121): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at account2.v(124): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at account2.v(129): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at account2.v(136): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at account2.v(142): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at account2.v(143): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at account2.v(155): truncated value with size 32 to match size of target (2)
Warning: Verilog HDL assignment warning at account2.v(157): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at account2.v(158): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at account2.v(183): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at account2.v(188): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at account2.v(210): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at account2.v(223): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at account2.v(224): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at account2.v(226): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at account2.v(230): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at account2.v(234): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at account2.v(238): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at account2.v(240): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at account2.v(241): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at account2.v(244): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at account2.v(255): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at account2.v(256): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at account2.v(258): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at account2.v(262): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at account2.v(263): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at account2.v(270): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at account2.v(272): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at account2.v(273): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at account2.v(275): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at account2.v(276): truncated value with size 32 to match size of target (1)
Warning: (10270) Verilog HDL statement warning at account2.v(215): incomplete Case Statement has no default case item
Info: Verilog HDL Case Statement information at account2.v(215): all case item expressions in this Case Statement are onehot; consider adding a full_case attribute to reduce the logic required to implement this Case Statement
Warning: Verilog HDL assignment warning at account2.v(281): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at account2.v(283): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at account2.v(292): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at account2.v(294): truncated value with size 32 to match size of target (1)
Info: Elaborating entity "clkdiv" for hierarchy "clkdiv:33"
Warning: Verilog HDL assignment warning at clkdiv.v(14): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at clkdiv.v(15): truncated value with size 32 to match size of target (23)
Warning: Verilog HDL assignment warning at clkdiv.v(19): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at clkdiv.v(20): truncated value with size 32 to match size of target (23)
Info: Elaborating entity "p7segment_new" for hierarchy "p7segment_new:inst4"
Info: Implemented 287 device resources after synthesis - the final resource count might be different
    Info: Implemented 7 input pins
    Info: Implemented 23 output pins
    Info: Implemented 257 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 55 warnings
    Info: Processing ended: Mon Mar 13 22:37:45 2006
    Info: Elapsed time: 00:00:15