phone.fit.summary

卡式计费电话电路,用verilogHDL编写,主要完成模拟真实电话的功能

Flow Status : Successful - Mon Mar 13 22:38:02 2006
Quartus II Version : 5.0 Build 168 06/22/2005 SP 1 SJ Full Version
Revision Name : phone
Top-level Entity Name : account_top
Family : Cyclone
Device : EP1C12Q240C8
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 255 / 12,060 ( 2 % )
Total pins : 30 / 173 ( 17 % )
Total virtual pins : 0
Total memory bits : 0 / 239,616 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )