📄 account_top1.rpt
字号:
|account1:38|lpm_add_sub:1285|altshift:oflow_ext_latency_ffs|
Device-Specific Information: e:\amj\eda\2003\experiment\phone\account_top1.rpt
account_top1
***** Logic for device 'account_top1' compiled without errors.
Device: EPF10K10LC84-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
^
C
R R R R R R R R R O
E E E E d d E E E E E N
S S S S e e V G G S G S S S S F
E E E E c c s C N N E N E E E E _ ^
R R R R i i t C c D D R D R R R R # D n
V V V V d d a I a I c I V I V V V V T O C
E E E E e e t N r N l N E N E E E E C N E
D D D D 0 1 e T d T k T D T D D D D K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | dp4
^nCE | 14 72 | dispmoneyhigh0
#TDI | 15 71 | dispmoneyhigh1
disptimehigh6 | 16 70 | dispmoneyhigh2
disptimehigh5 | 17 69 | dispmoneyhigh3
disptimehigh4 | 18 68 | GNDINT
disptimehigh3 | 19 67 | dispmoneyhigh4
VCCINT | 20 66 | dispmoneyhigh5
disptimehigh2 | 21 65 | dispmoneyhigh6
disptimehigh1 | 22 EPF10K10LC84-3 64 | RESERVED
disptimehigh0 | 23 63 | VCCINT
RESERVED | 24 62 | RESERVED
disptimelow6 | 25 61 | RESERVED
GNDINT | 26 60 | RESERVED
disptimelow5 | 27 59 | cut
disptimelow4 | 28 58 | warn
disptimelow3 | 29 57 | #TMS
disptimelow2 | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | read
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ d d R d d V G G G G V G d d d d d R w
C n i i E i i C N N N N C N i i i i i E r
C C s s S s s C D D D D C D s s s s s S i
I O p p E p p I I I I I I I p p p p p E t
N N t t R m m N N N N N N N m m m m m R e
T F i i V o o T T T T T T T o o o o o V
I m m E n n n n n n n E
G e e D e e e e e e e D
l l y y y y y y y
o o l l l l l l l
w w o o o o o o o
1 0 w w w w w w w
6 5 4 3 2 1 0
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\amj\eda\2003\experiment\phone\account_top1.rpt
account_top1
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 4/22( 18%)
A2 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 12/22( 54%)
A3 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 5/22( 22%)
A4 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
A5 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
A6 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 7/22( 31%)
A7 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 7/22( 31%)
A8 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 8/22( 36%)
A9 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 7/22( 31%)
A10 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 4/22( 18%)
A11 7/ 8( 87%) 2/ 8( 25%) 5/ 8( 62%) 2/2 0/2 5/22( 22%)
A12 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 13/22( 59%)
A13 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 6/22( 27%)
A14 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 6/22( 27%)
A15 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 0/2 0/2 6/22( 27%)
A16 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 2/22( 9%)
A17 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 10/22( 45%)
A18 6/ 8( 75%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
A19 2/ 8( 25%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 5/22( 22%)
A20 8/ 8(100%) 2/ 8( 25%) 7/ 8( 87%) 0/2 0/2 8/22( 36%)
A21 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
A22 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
A23 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 11/22( 50%)
A24 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
B1 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 13/22( 59%)
B2 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B3 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 12/22( 54%)
B5 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 0/2 0/2 7/22( 31%)
B8 8/ 8(100%) 1/ 8( 12%) 7/ 8( 87%) 0/2 0/2 6/22( 27%)
B9 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 13/22( 59%)
B10 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 11/22( 50%)
B11 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 11/22( 50%)
B12 3/ 8( 37%) 5/ 8( 62%) 3/ 8( 37%) 0/2 0/2 2/22( 9%)
B13 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
B16 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 9/22( 40%)
B18 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 5/22( 22%)
C1 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 6/22( 27%)
C2 3/ 8( 37%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 5/22( 22%)
C3 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
C4 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 12/22( 54%)
C5 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 8/22( 36%)
C6 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 5/22( 22%)
C7 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
C8 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 14/22( 63%)
C9 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 5/22( 22%)
C10 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 8/22( 36%)
C11 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 6/22( 27%)
C12 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 6/22( 27%)
C13 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 5/22( 22%)
C14 6/ 8( 75%) 0/ 8( 0%) 3/ 8( 37%) 2/2 0/2 9/22( 40%)
C15 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 6/22( 27%)
C16 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 7/22( 31%)
C17 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 8/22( 36%)
C18 6/ 8( 75%) 1/ 8( 12%) 4/ 8( 50%) 2/2 0/2 4/22( 18%)
C19 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 7/22( 31%)
C20 8/ 8(100%) 4/ 8( 50%) 2/ 8( 25%) 1/2 0/2 8/22( 36%)
C21 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
C22 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 7/22( 31%)
C23 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
C24 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
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