account_top1.rpt

卡式计费电话电路,用verilogHDL编写,主要完成模拟真实电话的功能

Project Information          e:\amj\eda\2003\experiment\phone\account_top1.rpt

MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 05/24/2003 16:02:53

Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

account_top1
      EPF10K10LC84-3       5      33     0    0         0  %    403      69 %

User Pins:                 5      33     0  



Project Information          e:\amj\eda\2003\experiment\phone\account_top1.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

account_top1@3                    card
account_top1@1                    clk
account_top1@59                   cut
account_top1@7                    decide0
account_top1@6                    decide1
account_top1@72                   dispmoneyhigh0
account_top1@71                   dispmoneyhigh1
account_top1@70                   dispmoneyhigh2
account_top1@69                   dispmoneyhigh3
account_top1@67                   dispmoneyhigh4
account_top1@66                   dispmoneyhigh5
account_top1@65                   dispmoneyhigh6
account_top1@51                   dispmoneylow0
account_top1@50                   dispmoneylow1
account_top1@49                   dispmoneylow2
account_top1@48                   dispmoneylow3
account_top1@47                   dispmoneylow4
account_top1@39                   dispmoneylow5
account_top1@38                   dispmoneylow6
account_top1@23                   disptimehigh0
account_top1@22                   disptimehigh1
account_top1@21                   disptimehigh2
account_top1@19                   disptimehigh3
account_top1@18                   disptimehigh4
account_top1@17                   disptimehigh5
account_top1@16                   disptimehigh6
account_top1@36                   disptimelow0
account_top1@35                   disptimelow1
account_top1@30                   disptimelow2
account_top1@29                   disptimelow3
account_top1@28                   disptimelow4
account_top1@27                   disptimelow5
account_top1@25                   disptimelow6
account_top1@73                   dp4
account_top1@54                   read
account_top1@5                    state
account_top1@58                   warn
account_top1@53                   write


Project Information          e:\amj\eda\2003\experiment\phone\account_top1.rpt

** FILE HIERARCHY **



|p7segment:12|
|p7segment:14|
|p7segment:10|
|p7segment:30|
|clkdiv:33|
|clkdiv:33|lpm_add_sub:201|
|clkdiv:33|lpm_add_sub:201|addcore:adder|
|clkdiv:33|lpm_add_sub:201|altshift:result_ext_latency_ffs|
|clkdiv:33|lpm_add_sub:201|altshift:carry_ext_latency_ffs|
|clkdiv:33|lpm_add_sub:201|altshift:oflow_ext_latency_ffs|
|account1:38|
|account1:38|lpm_add_sub:1274|
|account1:38|lpm_add_sub:1274|addcore:adder|
|account1:38|lpm_add_sub:1274|altshift:result_ext_latency_ffs|
|account1:38|lpm_add_sub:1274|altshift:carry_ext_latency_ffs|
|account1:38|lpm_add_sub:1274|altshift:oflow_ext_latency_ffs|
|account1:38|lpm_add_sub:1275|
|account1:38|lpm_add_sub:1275|addcore:adder|
|account1:38|lpm_add_sub:1275|altshift:result_ext_latency_ffs|
|account1:38|lpm_add_sub:1275|altshift:carry_ext_latency_ffs|
|account1:38|lpm_add_sub:1275|altshift:oflow_ext_latency_ffs|
|account1:38|lpm_add_sub:1276|
|account1:38|lpm_add_sub:1276|addcore:adder|
|account1:38|lpm_add_sub:1276|altshift:result_ext_latency_ffs|
|account1:38|lpm_add_sub:1276|altshift:carry_ext_latency_ffs|
|account1:38|lpm_add_sub:1276|altshift:oflow_ext_latency_ffs|
|account1:38|lpm_add_sub:1277|
|account1:38|lpm_add_sub:1277|addcore:adder|
|account1:38|lpm_add_sub:1277|altshift:result_ext_latency_ffs|
|account1:38|lpm_add_sub:1277|altshift:carry_ext_latency_ffs|
|account1:38|lpm_add_sub:1277|altshift:oflow_ext_latency_ffs|
|account1:38|lpm_add_sub:1278|
|account1:38|lpm_add_sub:1278|addcore:adder|
|account1:38|lpm_add_sub:1278|altshift:result_ext_latency_ffs|
|account1:38|lpm_add_sub:1278|altshift:carry_ext_latency_ffs|
|account1:38|lpm_add_sub:1278|altshift:oflow_ext_latency_ffs|
|account1:38|lpm_add_sub:1279|
|account1:38|lpm_add_sub:1279|addcore:adder|
|account1:38|lpm_add_sub:1279|altshift:result_ext_latency_ffs|
|account1:38|lpm_add_sub:1279|altshift:carry_ext_latency_ffs|
|account1:38|lpm_add_sub:1279|altshift:oflow_ext_latency_ffs|
|account1:38|lpm_add_sub:1280|
|account1:38|lpm_add_sub:1280|addcore:adder|
|account1:38|lpm_add_sub:1280|altshift:result_ext_latency_ffs|
|account1:38|lpm_add_sub:1280|altshift:carry_ext_latency_ffs|
|account1:38|lpm_add_sub:1280|altshift:oflow_ext_latency_ffs|
|account1:38|lpm_add_sub:1281|
|account1:38|lpm_add_sub:1281|addcore:adder|
|account1:38|lpm_add_sub:1281|altshift:result_ext_latency_ffs|
|account1:38|lpm_add_sub:1281|altshift:carry_ext_latency_ffs|
|account1:38|lpm_add_sub:1281|altshift:oflow_ext_latency_ffs|
|account1:38|lpm_add_sub:1282|
|account1:38|lpm_add_sub:1282|addcore:adder|
|account1:38|lpm_add_sub:1282|altshift:result_ext_latency_ffs|
|account1:38|lpm_add_sub:1282|altshift:carry_ext_latency_ffs|
|account1:38|lpm_add_sub:1282|altshift:oflow_ext_latency_ffs|
|account1:38|lpm_add_sub:1283|
|account1:38|lpm_add_sub:1283|addcore:adder|
|account1:38|lpm_add_sub:1283|altshift:result_ext_latency_ffs|
|account1:38|lpm_add_sub:1283|altshift:carry_ext_latency_ffs|
|account1:38|lpm_add_sub:1283|altshift:oflow_ext_latency_ffs|
|account1:38|lpm_add_sub:1284|
|account1:38|lpm_add_sub:1284|addcore:adder|
|account1:38|lpm_add_sub:1284|altshift:result_ext_latency_ffs|
|account1:38|lpm_add_sub:1284|altshift:carry_ext_latency_ffs|
|account1:38|lpm_add_sub:1284|altshift:oflow_ext_latency_ffs|
|account1:38|lpm_add_sub:1285|
|account1:38|lpm_add_sub:1285|addcore:adder|
|account1:38|lpm_add_sub:1285|altshift:result_ext_latency_ffs|
|account1:38|lpm_add_sub:1285|altshift:carry_ext_latency_ffs|