📄 account1.rpt
字号:
- 2 - A 02 OR2 s 0 4 0 1 ~585~2
- 6 - A 02 DFFE + 0 3 0 3 money7 (:586)
- 1 - A 12 DFFE + 0 3 0 6 money6 (:587)
- 6 - A 07 DFFE + 0 3 0 2 money5 (:588)
- 2 - A 10 DFFE + 0 3 0 5 money4 (:589)
- 5 - A 01 DFFE + 0 3 0 10 money3 (:590)
- 1 - A 04 DFFE + 0 3 0 10 money2 (:591)
- 5 - A 08 DFFE + 0 3 0 10 money1 (:592)
- 6 - A 04 DFFE + 0 3 0 5 money0 (:593)
- 8 - C 10 AND2 0 4 0 10 :594
- 8 - C 12 OR2 s 0 4 0 4 ~638~1
- 6 - C 12 OR2 0 4 0 2 :639
- 3 - C 12 OR2 0 4 0 2 :655
- 5 - C 12 OR2 0 4 0 1 :681
- 4 - C 09 OR2 0 4 0 1 :688
- 2 - C 12 OR2 0 4 0 1 :783
- 6 - C 09 OR2 0 4 0 1 :790
- 7 - C 09 OR2 0 4 0 1 :808
- 2 - C 09 OR2 s 0 4 0 1 ~809~1
- 3 - C 09 OR2 0 3 0 1 :809
- 5 - A 05 OR2 s 0 4 0 1 ~815~1
- 7 - A 05 OR2 0 4 0 1 :815
- 2 - B 09 OR2 s 0 2 0 4 ~843~1
- 4 - C 12 AND2 s 0 2 0 2 ~843~2
- 7 - C 07 OR2 s 0 3 0 1 ~843~3
- 8 - C 07 OR2 s 0 4 0 1 ~843~4
- 1 - C 12 AND2 s 0 4 0 1 ~843~5
- 4 - A 05 OR2 s 0 4 0 3 ~844~1
- 3 - C 07 AND2 s 0 4 0 1 ~844~2
- 5 - C 07 OR2 s 0 4 0 1 ~844~3
- 4 - C 10 AND2 s ! 0 3 0 1 ~845~1
- 6 - C 10 OR2 s 0 4 0 1 ~845~2
- 2 - C 10 OR2 s 0 4 0 1 ~846~1
- 1 - C 11 OR2 s 0 4 0 3 ~847~1
- 1 - C 10 OR2 s 0 4 0 1 ~847~2
- 2 - C 07 OR2 s 0 2 0 3 ~847~3
- 1 - C 09 DFFE + 0 3 1 5 dtime7 (:860)
- 5 - C 09 DFFE + 0 3 1 6 dtime6 (:861)
- 1 - C 07 DFFE + 0 3 1 3 dtime5 (:862)
- 4 - C 07 DFFE + 0 3 1 5 dtime4 (:863)
- 3 - C 10 DFFE + 0 3 1 2 dtime3 (:864)
- 7 - C 10 DFFE + 0 3 1 3 dtime2 (:865)
- 5 - C 10 DFFE + 0 3 1 4 dtime1 (:866)
- 6 - A 05 DFFE + 0 3 1 6 dtime0 (:867)
- 1 - A 02 AND2 1 1 1 0 :877
- 8 - A 13 AND2 1 1 1 0 :881
- 3 - A 07 AND2 1 1 1 0 :885
- 4 - A 07 AND2 1 1 1 0 :889
- 7 - A 07 AND2 1 1 1 0 :893
- 2 - A 22 AND2 1 1 1 0 :897
- 8 - A 07 AND2 1 1 1 0 :901
- 5 - A 07 AND2 1 1 1 0 :905
- 8 - C 09 AND2 0 2 0 3 :919
- 1 - A 05 AND2 0 2 0 4 :923
- 2 - A 09 OR2 s 2 0 0 13 ~926~1
- 8 - C 08 DFFE + 0 3 1 0 :935
- 4 - B 09 DFFE + 0 3 1 1 :968
- 3 - B 09 OR2 s 0 4 0 2 ~990~1
- 5 - B 09 AND2 s 0 2 0 2 ~990~2
- 7 - B 09 OR2 s 0 4 0 2 ~990~3
- 8 - B 09 DFFE + 0 3 0 2 reset_ena (:993)
- 5 - B 19 OR2 s 0 4 0 1 ~1001~1
- 4 - B 22 OR2 s 0 3 0 1 ~1001~2
- 1 - B 13 OR2 s 0 4 0 1 ~1001~3
- 4 - B 16 OR2 s 0 3 0 1 ~1001~4
- 1 - B 21 OR2 s 0 4 0 1 ~1001~5
- 1 - B 20 OR2 s 0 4 0 1 ~1001~6
- 3 - B 16 OR2 s 0 4 0 1 ~1001~7
- 5 - B 15 OR2 s 0 4 0 1 ~1001~8
- 5 - B 13 OR2 s 0 4 0 1 ~1001~9
- 2 - B 22 OR2 ! 0 4 0 5 :1001
- 8 - B 17 AND2 s 0 2 0 28 ~1171~1
- 6 - B 09 AND2 s 1 2 0 5 ~1202~1
- 8 - B 15 DFFE + 0 3 0 1 temp31 (:1235)
- 6 - B 15 DFFE + 0 3 0 2 temp30 (:1236)
- 4 - B 15 DFFE + 0 2 0 3 temp29 (:1237)
- 1 - B 15 DFFE + 0 3 0 2 temp28 (:1238)
- 2 - B 15 DFFE + 0 2 0 3 temp27 (:1239)
- 8 - B 13 DFFE + 0 3 0 2 temp26 (:1240)
- 7 - B 13 DFFE + 0 2 0 3 temp25 (:1241)
- 4 - B 13 DFFE + 0 3 0 2 temp24 (:1242)
- 3 - B 13 DFFE + 0 2 0 3 temp23 (:1243)
- 6 - B 16 DFFE + 0 3 0 2 temp22 (:1244)
- 5 - B 16 DFFE + 0 2 0 3 temp21 (:1245)
- 7 - B 16 DFFE + 0 3 0 2 temp20 (:1246)
- 2 - B 16 DFFE + 0 2 0 3 temp19 (:1247)
- 6 - B 21 DFFE + 0 2 0 2 temp18 (:1248)
- 3 - B 21 DFFE + 0 3 0 3 temp17 (:1249)
- 2 - B 21 DFFE + 0 2 0 4 temp16 (:1250)
- 6 - B 20 DFFE + 0 3 0 2 temp15 (:1251)
- 3 - B 20 DFFE + 0 3 0 3 temp14 (:1252)
- 2 - B 20 DFFE + 0 2 0 4 temp13 (:1253)
- 2 - B 19 DFFE + 0 3 0 2 temp12 (:1254)
- 8 - B 19 DFFE + 0 3 0 3 temp11 (:1255)
- 7 - B 19 DFFE + 0 2 0 4 temp10 (:1256)
- 6 - B 19 DFFE + 0 3 0 2 temp9 (:1257)
- 1 - B 24 DFFE + 0 3 0 3 temp8 (:1258)
- 8 - B 22 DFFE + 0 2 0 2 temp7 (:1259)
- 6 - B 22 DFFE + 0 3 0 3 temp6 (:1260)
- 5 - B 22 DFFE + 0 3 0 4 temp5 (:1261)
- 4 - B 17 DFFE + 0 3 0 2 temp4 (:1262)
- 7 - B 17 DFFE + 0 3 0 1 temp3 (:1263)
- 6 - B 17 DFFE + 0 2 0 2 temp2 (:1264)
- 3 - B 17 DFFE + 0 2 0 1 temp1 (:1265)
- 5 - B 17 DFFE + 0 1 0 2 temp0 (:1266)
- 1 - B 09 DFFE + 1 2 1 0 :1273
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\amj\eda\2003\experiment\phone\account1.rpt
account1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 9/ 96( 9%) 25/ 48( 52%) 2/ 48( 4%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
B: 6/ 96( 6%) 28/ 48( 58%) 20/ 48( 41%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
C: 6/ 96( 6%) 21/ 48( 43%) 0/ 48( 0%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 5/24( 20%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\amj\eda\2003\experiment\phone\account1.rpt
account1
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 86 clk
Device-Specific Information: e:\amj\eda\2003\experiment\phone\account1.rpt
account1
** EQUATIONS **
card : INPUT;
clk : INPUT;
decide0 : INPUT;
decide1 : INPUT;
state : INPUT;
-- Node name is 'cut'
-- Equation name is 'cut', type is output
cut = _LC1_B9;
-- Node name is 'dispmoney0'
-- Equation name is 'dispmoney0', type is output
dispmoney0 = _LC5_A7;
-- Node name is 'dispmoney1'
-- Equation name is 'dispmoney1', type is output
dispmoney1 = _LC8_A7;
-- Node name is 'dispmoney2'
-- Equation name is 'dispmoney2', type is output
dispmoney2 = _LC2_A22;
-- Node name is 'dispmoney3'
-- Equation name is 'dispmoney3', type is output
dispmoney3 = _LC7_A7;
-- Node name is 'dispmoney4'
-- Equation name is 'dispmoney4', type is output
dispmoney4 = _LC4_A7;
-- Node name is 'dispmoney5'
-- Equation name is 'dispmoney5', type is output
dispmoney5 = _LC3_A7;
-- Node name is 'dispmoney6'
-- Equation name is 'dispmoney6', type is output
dispmoney6 = _LC8_A13;
-- Node name is 'dispmoney7'
-- Equation name is 'dispmoney7', type is output
dispmoney7 = _LC1_A2;
-- Node name is 'disptime0'
-- Equation name is 'disptime0', type is output
disptime0 = dtime0;
-- Node name is 'disptime1'
-- Equation name is 'disptime1', type is output
disptime1 = dtime1;
-- Node name is 'disptime2'
-- Equation name is 'disptime2', type is output
disptime2 = dtime2;
-- Node name is 'disptime3'
-- Equation name is 'disptime3', type is output
disptime3 = dtime3;
-- Node name is 'disptime4'
-- Equation name is 'disptime4', type is output
disptime4 = dtime4;
-- Node name is 'disptime5'
-- Equation name is 'disptime5', type is output
disptime5 = dtime5;
-- Node name is 'disptime6'
-- Equation name is 'disptime6', type is output
disptime6 = dtime6;
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