📄 account1.rpt
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Total dedicated input pins used: 5/6 ( 83%)
Total I/O pins used: 21/53 ( 39%)
Total logic cells used: 238/576 ( 41%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.34/4 ( 83%)
Total fan-in: 795/2304 ( 34%)
Total input pins required: 5
Total input I/O cell registers required: 0
Total output pins required: 21
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 238
Total flipflops required: 86
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 58/ 576 ( 10%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 8 2 8 8 0 8 8 3 8 0 8 0 1 0 0 0 0 0 0 0 0 1 0 0 71/0
B: 6 8 4 0 7 8 0 8 8 6 8 8 0 8 0 8 8 8 0 8 6 6 8 0 1 132/0
C: 0 0 0 0 0 0 8 1 8 8 2 8 0 0 0 0 0 0 0 0 0 0 0 0 0 35/0
Total: 14 16 6 8 15 8 16 17 19 22 10 24 0 9 0 8 8 8 0 8 6 6 9 0 1 238/0
Device-Specific Information: e:\amj\eda\2003\experiment\phone\account1.rpt
account1
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
2 - - - -- INPUT 0 0 0 12 card
1 - - - -- INPUT G 0 0 0 0 clk
44 - - - -- INPUT 0 0 0 3 decide0
84 - - - -- INPUT 0 0 0 3 decide1
42 - - - -- INPUT 0 0 0 4 state
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\amj\eda\2003\experiment\phone\account1.rpt
account1
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
21 - - B -- OUTPUT 0 1 0 0 cut
18 - - A -- OUTPUT 0 1 0 0 dispmoney0
36 - - - 07 OUTPUT 0 1 0 0 dispmoney1
72 - - A -- OUTPUT 0 1 0 0 dispmoney2
19 - - A -- OUTPUT 0 1 0 0 dispmoney3
71 - - A -- OUTPUT 0 1 0 0 dispmoney4
17 - - A -- OUTPUT 0 1 0 0 dispmoney5
69 - - A -- OUTPUT 0 1 0 0 dispmoney6
16 - - A -- OUTPUT 0 1 0 0 dispmoney7
35 - - - 06 OUTPUT 0 1 0 0 disptime0
38 - - - 10 OUTPUT 0 1 0 0 disptime1
30 - - C -- OUTPUT 0 1 0 0 disptime2
28 - - C -- OUTPUT 0 1 0 0 disptime3
60 - - C -- OUTPUT 0 1 0 0 disptime4
27 - - C -- OUTPUT 0 1 0 0 disptime5
59 - - C -- OUTPUT 0 1 0 0 disptime6
62 - - C -- OUTPUT 0 1 0 0 disptime7
73 - - A -- OUTPUT 0 1 0 0 read
22 - - B -- OUTPUT 0 1 0 0 t1m
23 - - B -- OUTPUT 0 1 0 0 warn
29 - - C -- OUTPUT 0 1 0 0 write
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\amj\eda\2003\experiment\phone\account1.rpt
account1
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - B 06 AND2 0 2 0 5 |lpm_add_sub:1274|addcore:adder|:167
- 8 - B 06 AND2 0 3 0 4 |lpm_add_sub:1274|addcore:adder|:175
- 6 - B 11 AND2 0 2 0 1 |lpm_add_sub:1274|addcore:adder|:179
- 1 - B 11 AND2 0 4 0 2 |lpm_add_sub:1274|addcore:adder|:187
- 2 - B 11 AND2 0 2 0 3 |lpm_add_sub:1274|addcore:adder|:191
- 2 - B 02 AND2 0 3 0 4 |lpm_add_sub:1274|addcore:adder|:199
- 7 - B 02 AND2 0 2 0 1 |lpm_add_sub:1274|addcore:adder|:203
- 4 - B 02 AND2 0 4 0 4 |lpm_add_sub:1274|addcore:adder|:211
- 5 - B 01 AND2 0 2 0 1 |lpm_add_sub:1274|addcore:adder|:215
- 1 - B 01 AND2 0 4 0 4 |lpm_add_sub:1274|addcore:adder|:223
- 3 - B 10 AND2 0 2 0 1 |lpm_add_sub:1274|addcore:adder|:227
- 4 - B 10 AND2 0 4 0 3 |lpm_add_sub:1274|addcore:adder|:235
- 3 - B 05 AND2 0 3 0 3 |lpm_add_sub:1274|addcore:adder|:243
- 4 - B 05 AND2 0 3 0 3 |lpm_add_sub:1274|addcore:adder|:251
- 6 - B 08 AND2 0 3 0 3 |lpm_add_sub:1274|addcore:adder|:259
- 2 - B 08 AND2 0 3 0 3 |lpm_add_sub:1274|addcore:adder|:267
- 2 - B 12 AND2 0 3 0 3 |lpm_add_sub:1274|addcore:adder|:275
- 7 - B 12 AND2 0 2 0 1 |lpm_add_sub:1274|addcore:adder|:279
- 2 - A 07 AND2 ! 0 2 0 3 |lpm_add_sub:1276|addcore:adder|pcarry1
- 4 - A 02 AND2 ! 0 2 0 3 |lpm_add_sub:1276|addcore:adder|pcarry2
- 7 - C 12 AND2 0 3 0 1 |lpm_add_sub:1281|addcore:adder|:59
- 8 - A 05 AND2 0 2 0 1 |lpm_add_sub:1282|addcore:adder|:55
- 2 - B 17 AND2 0 2 0 3 |lpm_add_sub:1285|addcore:adder|:167
- 1 - B 17 AND2 0 3 0 3 |lpm_add_sub:1285|addcore:adder|:175
- 3 - B 22 AND2 0 2 0 4 |lpm_add_sub:1285|addcore:adder|:179
- 7 - B 22 AND2 0 3 0 1 |lpm_add_sub:1285|addcore:adder|:187
- 1 - B 22 AND2 0 4 0 3 |lpm_add_sub:1285|addcore:adder|:191
- 3 - B 19 AND2 0 3 0 4 |lpm_add_sub:1285|addcore:adder|:199
- 4 - B 19 AND2 0 2 0 1 |lpm_add_sub:1285|addcore:adder|:203
- 1 - B 19 AND2 0 4 0 4 |lpm_add_sub:1285|addcore:adder|:211
- 5 - B 20 AND2 0 2 0 1 |lpm_add_sub:1285|addcore:adder|:215
- 4 - B 20 AND2 0 4 0 4 |lpm_add_sub:1285|addcore:adder|:223
- 5 - B 21 AND2 0 3 0 1 |lpm_add_sub:1285|addcore:adder|:231
- 4 - B 21 AND2 0 4 0 3 |lpm_add_sub:1285|addcore:adder|:235
- 1 - B 16 AND2 0 3 0 3 |lpm_add_sub:1285|addcore:adder|:243
- 8 - B 16 AND2 0 3 0 3 |lpm_add_sub:1285|addcore:adder|:251
- 6 - B 13 AND2 0 3 0 3 |lpm_add_sub:1285|addcore:adder|:259
- 2 - B 13 AND2 0 3 0 3 |lpm_add_sub:1285|addcore:adder|:267
- 3 - B 15 AND2 0 3 0 3 |lpm_add_sub:1285|addcore:adder|:275
- 7 - B 15 AND2 0 2 0 1 |lpm_add_sub:1285|addcore:adder|:279
- 1 - A 07 LCELL s 1 0 1 0 read~1
- 4 - A 10 AND2 s 0 2 0 1 ~28~1
- 5 - A 02 AND2 s 0 3 0 1 ~28~2
- 2 - C 11 AND2 s 0 3 0 1 ~28~3
- 1 - B 03 AND2 2 0 0 15 :28
- 3 - B 02 OR2 s 0 4 0 1 ~29~1
- 5 - B 11 OR2 s 0 4 0 1 ~29~2
- 4 - B 06 OR2 s 0 4 0 2 ~29~3
- 3 - B 08 OR2 s 0 4 0 1 ~29~4
- 2 - B 05 OR2 s 0 4 0 1 ~29~5
- 5 - B 10 OR2 s 0 4 0 1 ~29~6
- 2 - B 01 OR2 s 0 4 0 1 ~29~7
- 1 - B 08 OR2 s 0 4 0 2 ~29~8
- 5 - B 12 OR2 s 0 4 0 2 ~29~9
- 1 - B 06 OR2 ! 0 4 0 2 :29
- 3 - B 03 AND2 s 1 1 0 30 ~165~1
- 8 - B 12 DFFE + 0 3 0 1 num131 (:199)
- 6 - B 12 DFFE + 0 3 0 2 num130 (:200)
- 3 - B 12 DFFE + 0 2 0 3 num129 (:201)
- 1 - B 12 DFFE + 0 3 0 2 num128 (:202)
- 4 - B 12 DFFE + 0 2 0 3 num127 (:203)
- 8 - B 08 DFFE + 0 3 0 2 num126 (:204)
- 7 - B 08 DFFE + 0 2 0 3 num125 (:205)
- 4 - B 08 DFFE + 0 3 0 2 num124 (:206)
- 5 - B 08 DFFE + 0 2 0 3 num123 (:207)
- 7 - B 05 DFFE + 0 3 0 2 num122 (:208)
- 6 - B 05 DFFE + 0 2 0 3 num121 (:209)
- 5 - B 05 DFFE + 0 3 0 2 num120 (:210)
- 1 - B 05 DFFE + 0 2 0 3 num119 (:211)
- 6 - B 10 DFFE + 0 3 0 2 num118 (:212)
- 2 - B 10 DFFE + 0 3 0 3 num117 (:213)
- 1 - B 10 DFFE + 0 2 0 4 num116 (:214)
- 6 - B 01 DFFE + 0 3 0 2 num115 (:215)
- 4 - B 01 DFFE + 0 3 0 3 num114 (:216)
- 3 - B 01 DFFE + 0 2 0 4 num113 (:217)
- 8 - B 02 DFFE + 0 3 0 2 num112 (:218)
- 6 - B 02 DFFE + 0 3 0 3 num111 (:219)
- 5 - B 02 DFFE + 0 2 0 4 num110 (:220)
- 1 - B 02 DFFE + 0 3 0 2 num19 (:221)
- 5 - B 03 DFFE + 1 2 0 3 num18 (:222)
- 8 - B 11 DFFE + 0 2 0 2 num17 (:223)
- 7 - B 11 DFFE + 0 3 0 2 num16 (:224)
- 4 - B 11 DFFE + 0 3 0 3 num15 (:225)
- 3 - B 11 DFFE + 0 2 0 4 num14 (:226)
- 6 - B 06 DFFE + 0 3 0 2 num13 (:227)
- 5 - B 06 DFFE + 0 2 0 3 num12 (:228)
- 7 - B 06 DFFE + 0 2 0 1 num11 (:229)
- 2 - B 03 DFFE + 1 0 0 2 num10 (:230)
- 2 - B 06 DFFE + 0 4 1 18 :234
- 5 - A 09 AND2 2 0 0 13 :235
- 8 - A 02 AND2 0 3 0 12 :249
- 8 - A 04 OR2 0 4 0 6 :287
- 2 - A 03 SOFT s ! 0 1 0 1 set~1 (~304~1)
- 1 - A 03 DFFE + 0 1 0 22 set (:304)
- 4 - A 01 AND2 0 2 0 1 :319
- 3 - A 05 AND2 0 2 0 1 :320
- 1 - A 08 AND2 0 2 0 4 :321
- 6 - A 12 OR2 0 2 0 1 :324
- 2 - A 12 OR2 0 4 0 1 :351
- 3 - A 01 OR2 0 4 0 1 :354
- 2 - A 04 OR2 0 4 0 1 :355
- 4 - A 08 OR2 0 3 0 1 :356
- 6 - A 08 OR2 0 3 0 1 :381
- 3 - A 12 OR2 0 4 0 1 :384
- 8 - A 09 AND2 2 0 0 11 :391
- 7 - A 02 AND2 0 3 0 11 :405
- 1 - A 01 OR2 0 3 0 7 :443
- 4 - A 12 OR2 0 4 0 1 :478
- 2 - A 01 OR2 0 4 0 1 :481
- 3 - A 04 OR2 0 3 0 1 :482
- 2 - A 08 OR2 0 3 0 1 :483
- 5 - A 12 OR2 0 4 0 1 :511
- 2 - A 05 OR2 0 4 0 1 :515
- 3 - A 08 OR2 0 4 0 1 :516
- 4 - A 04 AND2 0 3 0 1 :525
- 7 - A 12 OR2 0 4 0 1 :529
- 6 - A 01 OR2 s 0 4 0 1 ~532~1
- 7 - A 01 OR2 0 3 0 1 :532
- 5 - A 04 OR2 0 4 0 1 :533
- 7 - A 08 OR2 s 0 4 0 1 ~534~1
- 8 - A 12 OR2 0 4 0 1 :554
- 8 - A 01 OR2 0 4 0 1 :557
- 7 - A 04 OR2 0 4 0 1 :558
- 8 - A 08 OR2 0 4 0 1 :559
- 1 - A 10 AND2 s 0 2 0 2 ~580~1
- 3 - A 02 OR2 s 0 4 0 2 ~580~2
- 3 - A 10 OR2 s 0 4 0 1 ~581~1
- 5 - A 10 OR2 s 0 4 0 1 ~581~2
- 6 - A 10 OR2 s 0 4 0 1 ~581~3
- 7 - A 10 OR2 s 0 4 0 1 ~581~4
- 8 - A 10 OR2 s 0 4 0 2 ~581~5
- 6 - C 07 AND2 s ! 0 2 0 6 ~585~1
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