📄 account.rpt
字号:
- 2 - B 20 SOFT s ! 0 1 0 1 set~1 (~334~1)
- 1 - B 20 DFFE + 0 1 0 30 set (:334)
- 5 - B 24 AND2 0 2 0 1 :357
- 3 - B 13 AND2 0 2 0 1 :358
- 1 - B 06 OR2 0 2 0 3 :362
- 6 - B 03 OR2 0 2 0 1 :364
- 5 - B 05 OR2 0 4 0 2 :413
- 5 - B 06 OR2 0 3 0 1 :451
- 4 - B 03 OR2 0 4 0 1 :453
- 4 - B 24 OR2 0 4 0 1 :458
- 5 - B 13 OR2 0 4 0 1 :459
- 4 - B 14 OR2 0 3 0 1 :460
- 5 - B 14 OR2 0 4 0 1 :497
- 6 - B 06 OR2 0 4 0 1 :500
- 5 - B 03 OR2 0 4 0 1 :502
- 4 - C 18 AND2 2 0 0 11 :511
- 5 - B 12 AND2 0 4 0 11 :525
- 3 - B 16 OR2 0 3 0 10 :583
- 3 - B 06 OR2 0 3 0 1 :678
- 2 - B 03 OR2 0 4 0 1 :680
- 3 - B 24 OR2 0 4 0 1 :685
- 2 - B 13 OR2 0 3 0 1 :686
- 2 - B 14 OR2 0 3 0 1 :687
- 3 - B 14 OR2 0 4 0 1 :724
- 4 - B 06 OR2 0 4 0 1 :727
- 3 - B 03 OR2 0 4 0 1 :729
- 4 - B 13 OR2 0 4 0 1 :735
- 6 - B 13 AND2 0 3 0 1 :749
- 7 - B 06 OR2 0 4 0 1 :753
- 7 - B 03 OR2 0 4 0 1 :755
- 6 - B 24 OR2 s 0 4 0 1 ~760~1
- 7 - B 24 OR2 0 3 0 1 :760
- 7 - B 13 OR2 0 4 0 1 :761
- 6 - B 14 OR2 s 0 4 0 1 ~762~1
- 7 - B 14 OR2 0 4 0 1 :762
- 8 - B 06 OR2 0 4 0 1 :790
- 8 - B 03 OR2 0 4 0 1 :792
- 8 - B 24 OR2 0 4 0 1 :797
- 8 - B 13 OR2 0 4 0 1 :798
- 8 - B 14 OR2 0 4 0 1 :799
- 8 - B 12 OR2 s 0 4 0 1 ~826~1
- 1 - B 05 OR2 s 0 4 0 1 ~828~1
- 2 - B 12 OR2 s 0 4 0 2 ~828~2
- 7 - B 12 OR2 s 0 4 0 1 ~828~3
- 2 - B 08 OR2 s 0 3 0 2 ~832~1
- 7 - B 15 OR2 s 0 4 0 4 ~833~1
- 5 - B 15 OR2 s 0 4 0 1 ~833~2
- 8 - B 15 OR2 s 0 4 0 4 ~833~3
- 3 - B 05 OR2 s 0 2 0 1 ~833~4
- 6 - B 15 AND2 s ! 0 2 0 7 ~837~1
- 2 - B 15 OR2 s 0 4 0 1 ~837~2
- 6 - B 12 DFFE + 0 3 0 4 money11 (:838)
- 2 - B 06 DFFE + 0 3 0 5 money10 (:839)
- 3 - B 12 DFFE + 0 3 0 4 money9 (:840)
- 1 - B 03 DFFE + 0 3 0 8 money8 (:841)
- 2 - B 10 DFFE + 0 3 0 2 money7 (:842)
- 3 - B 10 DFFE + 0 3 0 3 money6 (:843)
- 6 - B 10 DFFE + 0 3 0 4 money5 (:844)
- 5 - B 10 DFFE + 0 2 0 5 money4 (:845)
- 2 - B 24 DFFE + 0 3 0 9 money3 (:846)
- 1 - B 13 DFFE + 0 3 0 10 money2 (:847)
- 1 - B 14 DFFE + 0 3 0 13 money1 (:848)
- 1 - B 15 DFFE + 0 3 0 5 money0 (:849)
- 1 - C 15 AND2 0 4 0 10 :850
- 4 - C 16 OR2 s 0 4 0 4 ~895~1
- 5 - C 16 OR2 0 4 0 2 :896
- 6 - C 16 OR2 0 4 0 2 :912
- 2 - C 16 OR2 0 4 0 1 :938
- 5 - C 23 OR2 0 4 0 1 :945
- 7 - C 16 OR2 0 4 0 1 :1041
- 6 - C 23 OR2 0 4 0 1 :1048
- 7 - C 23 OR2 0 4 0 1 :1066
- 3 - C 23 OR2 s 0 4 0 1 ~1067~1
- 4 - C 23 OR2 0 3 0 1 :1067
- 2 - B 21 OR2 s 0 4 0 1 ~1073~1
- 7 - B 21 OR2 0 4 0 1 :1073
- 6 - B 21 OR2 s 0 2 0 4 ~1101~1
- 3 - C 16 AND2 s 0 2 0 2 ~1101~2
- 4 - C 17 OR2 s 0 3 0 1 ~1101~3
- 6 - C 17 OR2 s 0 4 0 1 ~1101~4
- 1 - C 16 AND2 s 0 4 0 1 ~1101~5
- 3 - B 21 OR2 s 0 4 0 3 ~1102~1
- 1 - C 17 AND2 s 0 4 0 1 ~1102~2
- 2 - C 17 OR2 s 0 4 0 1 ~1102~3
- 8 - C 15 AND2 s ! 0 3 0 1 ~1103~1
- 3 - C 15 OR2 s 0 4 0 1 ~1103~2
- 6 - C 15 OR2 s 0 4 0 1 ~1104~1
- 1 - C 18 OR2 s 0 4 0 3 ~1105~1
- 2 - C 15 OR2 s 0 4 0 1 ~1105~2
- 8 - C 17 OR2 s 0 2 0 3 ~1105~3
- 2 - C 23 DFFE + 0 3 1 5 dtime7 (:1118)
- 1 - C 23 DFFE + 0 3 1 6 dtime6 (:1119)
- 3 - C 17 DFFE + 0 3 1 3 dtime5 (:1120)
- 7 - C 17 DFFE + 0 3 1 5 dtime4 (:1121)
- 5 - C 17 DFFE + 0 3 1 2 dtime3 (:1122)
- 4 - C 15 DFFE + 0 3 1 3 dtime2 (:1123)
- 7 - C 15 DFFE + 0 3 1 4 dtime1 (:1124)
- 1 - B 21 DFFE + 0 3 1 6 dtime0 (:1125)
- 1 - B 02 AND2 1 1 1 0 :1135
- 8 - B 05 AND2 1 1 1 0 :1139
- 4 - B 05 AND2 1 1 1 0 :1143
- 2 - B 05 AND2 1 1 1 0 :1147
- 6 - B 16 AND2 1 1 1 0 :1151
- 4 - B 16 AND2 1 1 1 0 :1155
- 2 - B 18 AND2 1 1 1 0 :1159
- 4 - B 10 AND2 1 1 1 0 :1163
- 5 - B 16 AND2 1 1 1 0 :1167
- 7 - B 16 AND2 1 1 1 0 :1171
- 2 - B 16 AND2 1 1 1 0 :1175
- 8 - B 16 AND2 1 1 1 0 :1179
- 4 - B 21 AND2 0 2 0 7 :1197
- 8 - B 21 AND2 0 2 0 6 :1201
- 5 - C 18 OR2 s 2 0 0 15 ~1204~1
- 3 - B 15 DFFE + 0 3 1 0 :1213
- 3 - C 05 DFFE + 0 3 1 1 :1246
- 5 - B 21 OR2 s 0 4 0 2 ~1268~1
- 2 - C 05 AND2 s 0 2 0 2 ~1268~2
- 7 - C 05 OR2 s 0 4 0 2 ~1268~3
- 8 - C 05 DFFE + 0 3 0 2 reset_ena (:1271)
- 5 - C 07 OR2 s 0 4 0 1 ~1279~1
- 4 - C 08 OR2 s 0 3 0 1 ~1279~2
- 1 - C 11 OR2 s 0 4 0 1 ~1279~3
- 3 - C 02 OR2 s 0 3 0 1 ~1279~4
- 1 - C 06 OR2 s 0 4 0 1 ~1279~5
- 8 - C 01 OR2 s 0 4 0 1 ~1279~6
- 2 - C 02 OR2 s 0 4 0 1 ~1279~7
- 8 - C 12 OR2 s 0 4 0 1 ~1279~8
- 5 - C 11 OR2 s 0 4 0 1 ~1279~9
- 2 - C 08 OR2 ! 0 4 0 5 :1279
- 4 - C 05 AND2 s 0 2 0 28 ~1449~1
- 1 - C 05 AND2 s 1 2 0 5 ~1480~1
- 7 - C 12 DFFE + 0 3 0 1 temp31 (:1513)
- 4 - C 12 DFFE + 0 3 0 2 temp30 (:1514)
- 3 - C 12 DFFE + 0 2 0 3 temp29 (:1515)
- 1 - C 12 DFFE + 0 3 0 2 temp28 (:1516)
- 6 - C 12 DFFE + 0 2 0 3 temp27 (:1517)
- 8 - C 11 DFFE + 0 3 0 2 temp26 (:1518)
- 6 - C 11 DFFE + 0 2 0 3 temp25 (:1519)
- 3 - C 11 DFFE + 0 3 0 2 temp24 (:1520)
- 7 - C 11 DFFE + 0 2 0 3 temp23 (:1521)
- 7 - C 02 DFFE + 0 3 0 2 temp22 (:1522)
- 6 - C 02 DFFE + 0 2 0 3 temp21 (:1523)
- 8 - C 02 DFFE + 0 3 0 2 temp20 (:1524)
- 5 - C 02 DFFE + 0 2 0 3 temp19 (:1525)
- 6 - C 06 DFFE + 0 2 0 2 temp18 (:1526)
- 3 - C 06 DFFE + 0 3 0 3 temp17 (:1527)
- 2 - C 06 DFFE + 0 2 0 4 temp16 (:1528)
- 5 - C 01 DFFE + 0 3 0 2 temp15 (:1529)
- 3 - C 01 DFFE + 0 3 0 3 temp14 (:1530)
- 1 - C 01 DFFE + 0 2 0 4 temp13 (:1531)
- 4 - C 07 DFFE + 0 3 0 2 temp12 (:1532)
- 8 - C 07 DFFE + 0 3 0 3 temp11 (:1533)
- 7 - C 07 DFFE + 0 2 0 4 temp10 (:1534)
- 6 - C 07 DFFE + 0 3 0 2 temp9 (:1535)
- 6 - C 05 DFFE + 0 3 0 3 temp8 (:1536)
- 8 - C 08 DFFE + 0 2 0 2 temp7 (:1537)
- 6 - C 08 DFFE + 0 3 0 3 temp6 (:1538)
- 5 - C 08 DFFE + 0 3 0 4 temp5 (:1539)
- 8 - C 10 DFFE + 0 3 0 2 temp4 (:1540)
- 6 - C 10 DFFE + 0 3 0 1 temp3 (:1541)
- 5 - C 10 DFFE + 0 2 0 2 temp2 (:1542)
- 3 - C 10 DFFE + 0 2 0 1 temp1 (:1543)
- 4 - C 10 DFFE + 0 1 0 2 temp0 (:1544)
- 5 - C 05 DFFE + 1 2 1 0 :1551
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\amj\eda\2003\experiment\phone\account.rpt
account
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 0/ 48( 0%) 23/ 48( 47%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 20/ 96( 20%) 12/ 48( 25%) 11/ 48( 22%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
C: 13/ 96( 13%) 23/ 48( 47%) 17/ 48( 35%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\amj\eda\2003\experiment\phone\account.rpt
account
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 90 clk
Device-Specific Information: e:\amj\eda\2003\experiment\phone\account.rpt
account
** EQUATIONS **
card : INPUT;
clk : INPUT;
decide0 : INPUT;
decide1 : INPUT;
state : INPUT;
-- Node name is 'cut'
-- Equation name is 'cut', type is output
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