📄 account.rpt
字号:
B14 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 12/22( 54%)
B15 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 10/22( 45%)
B16 8/ 8(100%) 3/ 8( 37%) 5/ 8( 62%) 0/2 0/2 7/22( 31%)
B18 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
B20 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 0/22( 0%)
B21 8/ 8(100%) 4/ 8( 50%) 4/ 8( 50%) 1/2 0/2 7/22( 31%)
B24 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 10/22( 45%)
C1 6/ 8( 75%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
C2 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 5/22( 22%)
C5 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 0/2 9/22( 40%)
C6 6/ 8( 75%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
C7 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 3/22( 13%)
C8 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 6/22( 27%)
C10 7/ 8( 87%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
C11 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 6/22( 27%)
C12 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 2/22( 9%)
C15 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
C16 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 9/22( 40%)
C17 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 9/22( 40%)
C18 5/ 8( 62%) 3/ 8( 37%) 4/ 8( 50%) 0/2 0/2 5/22( 22%)
C23 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 10/22( 45%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 5/6 ( 83%)
Total I/O pins used: 25/53 ( 47%)
Total logic cells used: 260/576 ( 45%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.35/4 ( 83%)
Total fan-in: 871/2304 ( 37%)
Total input pins required: 5
Total input I/O cell registers required: 0
Total output pins required: 25
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 260
Total flipflops required: 90
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 61/ 576 ( 10%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 8 7 0 7 7 8 0 2 8 8 63/0
B: 0 1 8 0 7 8 0 3 0 8 0 8 0 8 8 8 8 0 1 0 2 8 0 0 8 94/0
C: 6 8 0 0 8 6 8 8 0 7 8 8 0 0 0 8 8 8 5 0 0 0 0 7 0 103/0
Total: 6 9 8 0 15 14 8 11 0 15 8 16 0 16 8 24 23 8 13 7 10 8 2 15 16 260/0
Device-Specific Information: e:\amj\eda\2003\experiment\phone\account.rpt
account
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
2 - - - -- INPUT 0 0 0 16 card
1 - - - -- INPUT G 0 0 0 0 clk
44 - - - -- INPUT 0 0 0 3 decide0
84 - - - -- INPUT 0 0 0 3 decide1
42 - - - -- INPUT 0 0 0 4 state
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\amj\eda\2003\experiment\phone\account.rpt
account
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
29 - - C -- OUTPUT 0 1 0 0 cut
48 - - - 15 OUTPUT 0 1 0 0 dispmoney0
72 - - A -- OUTPUT 0 1 0 0 dispmoney1
64 - - B -- OUTPUT 0 1 0 0 dispmoney2
65 - - B -- OUTPUT 0 1 0 0 dispmoney3
38 - - - 10 OUTPUT 0 1 0 0 dispmoney4
51 - - - 18 OUTPUT 0 1 0 0 dispmoney5
49 - - - 16 OUTPUT 0 1 0 0 dispmoney6
24 - - B -- OUTPUT 0 1 0 0 dispmoney7
22 - - B -- OUTPUT 0 1 0 0 dispmoney8
23 - - B -- OUTPUT 0 1 0 0 dispmoney9
25 - - B -- OUTPUT 0 1 0 0 dispmoney10
21 - - B -- OUTPUT 0 1 0 0 dispmoney11
54 - - - 21 OUTPUT 0 1 0 0 disptime0
30 - - C -- OUTPUT 0 1 0 0 disptime1
60 - - C -- OUTPUT 0 1 0 0 disptime2
59 - - C -- OUTPUT 0 1 0 0 disptime3
58 - - C -- OUTPUT 0 1 0 0 disptime4
61 - - C -- OUTPUT 0 1 0 0 disptime5
27 - - C -- OUTPUT 0 1 0 0 disptime6
80 - - - 23 OUTPUT 0 1 0 0 disptime7
67 - - B -- OUTPUT 0 1 0 0 read
78 - - - 24 OUTPUT 0 1 0 0 t1m
28 - - C -- OUTPUT 0 1 0 0 warn
66 - - B -- OUTPUT 0 1 0 0 write
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\amj\eda\2003\experiment\phone\account.rpt
account
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - A 23 AND2 0 2 0 5 |lpm_add_sub:1552|addcore:adder|:167
- 4 - A 23 AND2 0 3 0 4 |lpm_add_sub:1552|addcore:adder|:175
- 6 - A 24 AND2 0 2 0 1 |lpm_add_sub:1552|addcore:adder|:179
- 3 - A 24 AND2 0 4 0 2 |lpm_add_sub:1552|addcore:adder|:187
- 1 - A 24 AND2 0 2 0 3 |lpm_add_sub:1552|addcore:adder|:191
- 5 - A 20 AND2 0 3 0 4 |lpm_add_sub:1552|addcore:adder|:199
- 8 - A 20 AND2 0 2 0 1 |lpm_add_sub:1552|addcore:adder|:203
- 4 - A 20 AND2 0 4 0 4 |lpm_add_sub:1552|addcore:adder|:211
- 5 - A 18 AND2 0 2 0 1 |lpm_add_sub:1552|addcore:adder|:215
- 2 - A 18 AND2 0 4 0 4 |lpm_add_sub:1552|addcore:adder|:223
- 7 - A 13 AND2 0 2 0 1 |lpm_add_sub:1552|addcore:adder|:227
- 1 - A 13 AND2 0 4 0 3 |lpm_add_sub:1552|addcore:adder|:235
- 1 - A 19 AND2 0 3 0 3 |lpm_add_sub:1552|addcore:adder|:243
- 8 - A 19 AND2 0 3 0 3 |lpm_add_sub:1552|addcore:adder|:251
- 5 - A 16 AND2 0 3 0 3 |lpm_add_sub:1552|addcore:adder|:259
- 1 - A 16 AND2 0 3 0 3 |lpm_add_sub:1552|addcore:adder|:267
- 3 - A 15 AND2 0 3 0 3 |lpm_add_sub:1552|addcore:adder|:275
- 7 - A 15 AND2 0 2 0 1 |lpm_add_sub:1552|addcore:adder|:279
- 7 - B 10 OR2 0 2 0 1 |lpm_add_sub:1554|addcore:adder|pcarry1
- 8 - B 10 OR2 0 3 0 1 |lpm_add_sub:1554|addcore:adder|pcarry2
- 6 - B 05 OR2 0 2 0 1 |lpm_add_sub:1555|addcore:adder|pcarry1
- 1 - B 12 AND2 ! 0 3 0 3 |lpm_add_sub:1555|addcore:adder|pcarry2
- 8 - C 16 AND2 0 3 0 1 |lpm_add_sub:1561|addcore:adder|:59
- 5 - C 15 AND2 0 2 0 1 |lpm_add_sub:1562|addcore:adder|:55
- 2 - C 10 AND2 0 2 0 3 |lpm_add_sub:1565|addcore:adder|:167
- 1 - C 10 AND2 0 3 0 3 |lpm_add_sub:1565|addcore:adder|:175
- 3 - C 08 AND2 0 2 0 4 |lpm_add_sub:1565|addcore:adder|:179
- 7 - C 08 AND2 0 3 0 1 |lpm_add_sub:1565|addcore:adder|:187
- 1 - C 08 AND2 0 4 0 3 |lpm_add_sub:1565|addcore:adder|:191
- 2 - C 07 AND2 0 3 0 4 |lpm_add_sub:1565|addcore:adder|:199
- 3 - C 07 AND2 0 2 0 1 |lpm_add_sub:1565|addcore:adder|:203
- 1 - C 07 AND2 0 4 0 4 |lpm_add_sub:1565|addcore:adder|:211
- 4 - C 01 AND2 0 2 0 1 |lpm_add_sub:1565|addcore:adder|:215
- 2 - C 01 AND2 0 4 0 4 |lpm_add_sub:1565|addcore:adder|:223
- 5 - C 06 AND2 0 3 0 1 |lpm_add_sub:1565|addcore:adder|:231
- 4 - C 06 AND2 0 4 0 3 |lpm_add_sub:1565|addcore:adder|:235
- 1 - C 02 AND2 0 3 0 3 |lpm_add_sub:1565|addcore:adder|:243
- 4 - C 02 AND2 0 3 0 3 |lpm_add_sub:1565|addcore:adder|:251
- 4 - C 11 AND2 0 3 0 3 |lpm_add_sub:1565|addcore:adder|:259
- 2 - C 11 AND2 0 3 0 3 |lpm_add_sub:1565|addcore:adder|:267
- 2 - C 12 AND2 0 3 0 3 |lpm_add_sub:1565|addcore:adder|:275
- 5 - C 12 AND2 0 2 0 1 |lpm_add_sub:1565|addcore:adder|:279
- 1 - B 16 LCELL s 1 0 1 0 read~1
- 4 - B 15 AND2 s 0 2 0 1 ~32~1
- 1 - B 08 AND2 s 0 3 0 1 ~32~2
- 3 - B 08 AND2 s 0 3 0 1 ~32~3
- 2 - C 18 AND2 s 0 3 0 1 ~32~4
- 2 - A 22 AND2 2 0 0 16 :32
- 3 - A 20 OR2 s 0 4 0 1 ~33~1
- 2 - A 24 OR2 s 0 4 0 1 ~33~2
- 3 - A 23 OR2 s 0 4 0 2 ~33~3
- 2 - A 16 OR2 s 0 4 0 1 ~33~4
- 2 - A 19 OR2 s 0 4 0 1 ~33~5
- 4 - A 13 OR2 s 0 4 0 1 ~33~6
- 1 - A 18 OR2 s 0 4 0 1 ~33~7
- 8 - A 18 OR2 s 0 4 0 2 ~33~8
- 4 - A 15 OR2 s 0 4 0 2 ~33~9
- 1 - A 23 OR2 ! 0 4 0 2 :33
- 3 - A 13 AND2 s 1 1 0 30 ~169~1
- 8 - A 15 DFFE + 0 3 0 1 num131 (:203)
- 6 - A 15 DFFE + 0 3 0 2 num130 (:204)
- 5 - A 15 DFFE + 0 2 0 3 num129 (:205)
- 2 - A 15 DFFE + 0 3 0 2 num128 (:206)
- 1 - A 15 DFFE + 0 2 0 3 num127 (:207)
- 7 - A 16 DFFE + 0 3 0 2 num126 (:208)
- 6 - A 16 DFFE + 0 2 0 3 num125 (:209)
- 4 - A 16 DFFE + 0 3 0 2 num124 (:210)
- 3 - A 16 DFFE + 0 2 0 3 num123 (:211)
- 6 - A 19 DFFE + 0 3 0 2 num122 (:212)
- 4 - A 19 DFFE + 0 2 0 3 num121 (:213)
- 3 - A 19 DFFE + 0 3 0 2 num120 (:214)
- 5 - A 19 DFFE + 0 2 0 3 num119 (:215)
- 8 - A 13 DFFE + 0 3 0 2 num118 (:216)
- 6 - A 13 DFFE + 0 3 0 3 num117 (:217)
- 5 - A 13 DFFE + 0 2 0 4 num116 (:218)
- 6 - A 18 DFFE + 0 3 0 2 num115 (:219)
- 4 - A 18 DFFE + 0 3 0 3 num114 (:220)
- 3 - A 18 DFFE + 0 2 0 4 num113 (:221)
- 1 - A 20 DFFE + 0 3 0 2 num112 (:222)
- 7 - A 20 DFFE + 0 3 0 3 num111 (:223)
- 6 - A 20 DFFE + 0 2 0 4 num110 (:224)
- 2 - A 20 DFFE + 0 3 0 2 num19 (:225)
- 2 - A 13 DFFE + 1 2 0 3 num18 (:226)
- 8 - A 24 DFFE + 0 2 0 2 num17 (:227)
- 7 - A 24 DFFE + 0 3 0 2 num16 (:228)
- 5 - A 24 DFFE + 0 3 0 3 num15 (:229)
- 4 - A 24 DFFE + 0 2 0 4 num14 (:230)
- 6 - A 23 DFFE + 0 3 0 2 num13 (:231)
- 5 - A 23 DFFE + 0 2 0 3 num12 (:232)
- 8 - A 23 DFFE + 0 2 0 1 num11 (:233)
- 8 - A 22 DFFE + 1 0 0 2 num10 (:234)
- 7 - A 23 DFFE + 0 4 1 19 :238
- 8 - C 18 AND2 2 0 0 11 :239
- 4 - B 12 AND2 0 4 0 10 :253
- 1 - B 24 OR2 0 4 0 8 :311
- 1 - B 10 AND2 0 4 0 11 :326
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