📄 alarm.rpt
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-- Node name is ':298'
-- Equation name is '_LC4_A4', type is buried
!_LC4_A4 = _LC4_A4~NOT;
_LC4_A4~NOT = LCELL( _EQ040);
_EQ040 = !_LC3_A4 & !sec2 & !sec3 & !sec4;
-- Node name is '~329~1'
-- Equation name is '~329~1', location is LC2_A17, type is buried.
-- synthesized logic cell
_LC2_A17 = LCELL( _EQ041);
_EQ041 = !sec6 & !sec7;
-- Node name is '~329~2'
-- Equation name is '~329~2', location is LC6_A18, type is buried.
-- synthesized logic cell
_LC6_A18 = LCELL( _EQ042);
_EQ042 = _LC3_A13 & _LC8_A14 & min0 & min4
# !_LC3_A13 & _LC8_A14 & min0 & !min4
# _LC3_A13 & !_LC8_A14 & !min0 & min4
# !_LC3_A13 & !_LC8_A14 & !min0 & !min4;
-- Node name is '~329~3'
-- Equation name is '~329~3', location is LC6_A14, type is buried.
-- synthesized logic cell
_LC6_A14 = LCELL( _EQ043);
_EQ043 = hour0 & hour5 & _LC1_A14 & _LC3_A21
# hour0 & !hour5 & _LC1_A14 & !_LC3_A21
# !hour0 & hour5 & !_LC1_A14 & _LC3_A21
# !hour0 & !hour5 & !_LC1_A14 & !_LC3_A21;
-- Node name is '~329~4'
-- Equation name is '~329~4', location is LC4_A24, type is buried.
-- synthesized logic cell
_LC4_A24 = LCELL( _EQ044);
_EQ044 = _LC2_A24 & _LC7_A24 & min1 & min2
# _LC2_A24 & !_LC7_A24 & min1 & !min2
# !_LC2_A24 & _LC7_A24 & !min1 & min2
# !_LC2_A24 & !_LC7_A24 & !min1 & !min2;
-- Node name is '~329~5'
-- Equation name is '~329~5', location is LC8_A21, type is buried.
-- synthesized logic cell
_LC8_A21 = LCELL( _EQ045);
_EQ045 = hour3 & hour7 & _LC1_A16 & _LC7_A21
# hour3 & !hour7 & _LC1_A16 & !_LC7_A21
# !hour3 & hour7 & !_LC1_A16 & _LC7_A21
# !hour3 & !hour7 & !_LC1_A16 & !_LC7_A21;
-- Node name is '~329~6'
-- Equation name is '~329~6', location is LC2_A21, type is buried.
-- synthesized logic cell
_LC2_A21 = LCELL( _EQ046);
_EQ046 = !_LC4_A4 & _LC4_A24 & _LC8_A21
# _LC4_A24 & _LC8_A21 & !sec5;
-- Node name is '~329~7'
-- Equation name is '~329~7', location is LC7_A18, type is buried.
-- synthesized logic cell
_LC7_A18 = LCELL( _EQ047);
_EQ047 = hour1 & _LC4_A13 & _LC6_A16 & min7
# !hour1 & _LC4_A13 & !_LC6_A16 & min7
# hour1 & !_LC4_A13 & _LC6_A16 & !min7
# !hour1 & !_LC4_A13 & !_LC6_A16 & !min7;
-- Node name is '~329~8'
-- Equation name is '~329~8', location is LC1_A18, type is buried.
-- synthesized logic cell
_LC1_A18 = LCELL( _EQ048);
_EQ048 = _LC2_A21 & _LC6_A14 & _LC6_A18 & _LC7_A18;
-- Node name is '~329~9'
-- Equation name is '~329~9', location is LC3_A14, type is buried.
-- synthesized logic cell
_LC3_A14 = LCELL( _EQ049);
_EQ049 = !disp_mode0 & _LC1_A24 & min3 & !set
# !disp_mode0 & !_LC1_A24 & !min3 & !set;
-- Node name is '~329~10'
-- Equation name is '~329~10', location is LC1_A22, type is buried.
-- synthesized logic cell
_LC1_A22 = LCELL( _EQ050);
_EQ050 = hour6 & _LC1_A21 & _LC5_A13 & min5
# hour6 & _LC1_A21 & !_LC5_A13 & !min5
# !hour6 & !_LC1_A21 & _LC5_A13 & min5
# !hour6 & !_LC1_A21 & !_LC5_A13 & !min5;
-- Node name is '~329~11'
-- Equation name is '~329~11', location is LC2_A22, type is buried.
-- synthesized logic cell
_LC2_A22 = LCELL( _EQ051);
_EQ051 = hour2 & hour4 & _LC5_A21 & _LC8_A16
# hour2 & !hour4 & !_LC5_A21 & _LC8_A16
# !hour2 & hour4 & _LC5_A21 & !_LC8_A16
# !hour2 & !hour4 & !_LC5_A21 & !_LC8_A16;
-- Node name is '~329~12'
-- Equation name is '~329~12', location is LC8_A17, type is buried.
-- synthesized logic cell
_LC8_A17 = LCELL( _EQ052);
_EQ052 = !disp_mode1 & _LC1_A13 & _LC2_A17 & min6
# !disp_mode1 & !_LC1_A13 & _LC2_A17 & !min6;
-- Node name is '~329~13'
-- Equation name is '~329~13', location is LC4_A22, type is buried.
-- synthesized logic cell
_LC4_A22 = LCELL( _EQ053);
_EQ053 = _LC1_A22 & _LC2_A22 & _LC3_A14 & _LC8_A17;
-- Node name is ':351'
-- Equation name is '_LC6_A17', type is buried
_LC6_A17 = LCELL( _EQ054);
_EQ054 = _LC1_A4 & sec6
# sec5 & sec6
# sec7;
-- Node name is ':363'
-- Equation name is '_LC1_A4', type is buried
_LC1_A4 = LCELL( _EQ055);
_EQ055 = sec1 & sec2 & sec4
# sec3 & sec4;
-- Node name is '~388~1'
-- Equation name is '~388~1', location is LC5_A17, type is buried.
-- synthesized logic cell
_LC5_A17 = LCELL( _EQ056);
_EQ056 = min0 & min3 & min4 & min6;
-- Node name is '~389~1'
-- Equation name is '~389~1', location is LC1_A17, type is buried.
-- synthesized logic cell
_LC1_A17 = LCELL( _EQ057);
_EQ057 = !min0 & !min3 & !min4 & !min6;
-- Node name is '~389~2'
-- Equation name is '~389~2', location is LC4_A17, type is buried.
-- synthesized logic cell
_LC4_A17 = LCELL( _EQ058);
_EQ058 = _LC1_A17 & _LC2_A17 & !_LC4_A4 & !sec5;
-- Node name is ':394'
-- Equation name is '_LC3_A17', type is buried
_LC3_A17 = LCELL( _EQ059);
_EQ059 = sec7
# sec5 & sec6
# _LC2_A4 & sec6;
-- Node name is ':406'
-- Equation name is '_LC2_A4', type is buried
_LC2_A4 = LCELL( _EQ060);
_EQ060 = sec3 & sec4
# _LC3_A4 & sec2 & sec4;
-- Node name is ':424'
-- Equation name is '_LC3_A4', type is buried
_LC3_A4 = LCELL( _EQ061);
_EQ061 = sec1
# sec0;
-- Node name is ':447'
-- Equation name is '_LC4_A18', type is buried
_LC4_A18 = DFFE( _EQ062, GLOBAL( clk_4Hz), VCC, VCC, VCC);
_EQ062 = sound0 & sound1;
-- Node name is '~455~1'
-- Equation name is '~455~1', location is LC5_A18, type is buried.
-- synthesized logic cell
_LC5_A18 = LCELL( _EQ063);
_EQ063 = clk_1KHz & !min1 & !min2 & !min7;
-- Node name is '~455~2'
-- Equation name is '~455~2', location is LC8_A18, type is buried.
-- synthesized logic cell
_LC8_A18 = LCELL( _EQ064);
_EQ064 = !_LC3_A17 & !_LC4_A18 & _LC5_A18 & !min5
# _LC3_A17 & _LC4_A18 & _LC5_A18 & !min5;
-- Node name is ':459'
-- Equation name is '_LC7_A17', type is buried
_LC7_A17 = DFFE( _EQ065, GLOBAL( clk_4Hz), VCC, VCC, VCC);
_EQ065 = _LC4_A17 & _LC8_A18
# _LC5_A17 & _LC6_A17 & _LC8_A18;
-- Node name is ':461'
-- Equation name is '_LC3_A22', type is buried
_LC3_A22 = LCELL( _EQ066);
_EQ066 = alarm1 & clk_4Hz
# _LC7_A17;
Project Information e:\amj\eda\experiment\calendar_clock\alarm.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 39,119K
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