📄 alarm.rpt
字号:
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\amj\eda\experiment\calendar_clock\alarm.rpt
alarm
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
67 - - B -- OUTPUT 0 1 0 0 ahour0
30 - - C -- OUTPUT 0 1 0 0 ahour1
69 - - A -- OUTPUT 0 1 0 0 ahour2
62 - - C -- OUTPUT 0 1 0 0 ahour3
59 - - C -- OUTPUT 0 1 0 0 ahour4
72 - - A -- OUTPUT 0 1 0 0 ahour5
54 - - - 21 OUTPUT 0 1 0 0 ahour6
19 - - A -- OUTPUT 0 1 0 0 ahour7
61 - - C -- OUTPUT 0 1 0 0 alarm
58 - - C -- OUTPUT 0 1 0 0 alarm2
65 - - B -- OUTPUT 0 1 0 0 amin0
28 - - C -- OUTPUT 0 1 0 0 amin1
64 - - B -- OUTPUT 0 1 0 0 amin2
73 - - A -- OUTPUT 0 1 0 0 amin3
66 - - B -- OUTPUT 0 1 0 0 amin4
70 - - A -- OUTPUT 0 1 0 0 amin5
27 - - C -- OUTPUT 0 1 0 0 amin6
71 - - A -- OUTPUT 0 1 0 0 amin7
60 - - C -- OUTPUT 0 1 0 0 ear
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\amj\eda\experiment\calendar_clock\alarm.rpt
alarm
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - A 13 AND2 0 2 0 1 |lpm_add_sub:463|addcore:adder|:55
- 8 - A 13 AND2 0 3 0 1 |lpm_add_sub:463|addcore:adder|:59
- 8 - A 24 AND2 0 2 0 1 |lpm_add_sub:464|addcore:adder|:55
- 4 - A 21 AND2 0 2 0 1 |lpm_add_sub:465|addcore:adder|:55
- 6 - A 21 AND2 0 3 0 1 |lpm_add_sub:465|addcore:adder|:59
- 4 - A 16 OR2 ! 0 2 0 3 |lpm_add_sub:466|addcore:adder|:55
- 5 - A 14 AND2 2 0 0 5 :51
- 2 - A 13 OR2 s 0 3 0 1 ~55~1
- 5 - A 24 OR2 ! 0 4 0 6 :73
- 6 - A 13 OR2 s 0 4 0 4 ~120~1
- 6 - A 24 AND2 s 0 2 0 3 ~124~1
- 4 - A 13 DFFE + 0 3 1 3 :145
- 1 - A 13 DFFE + 0 3 1 4 :146
- 5 - A 13 DFFE + 0 3 1 5 :147
- 3 - A 13 DFFE + 0 2 1 6 :148
- 1 - A 24 DFFE + 0 3 1 3 :149
- 7 - A 24 DFFE + 0 3 1 4 :150
- 2 - A 24 DFFE + 0 2 1 5 :151
- 8 - A 14 DFFE + 0 1 1 6 :152
- 5 - A 16 OR2 s 0 3 0 1 ~157~1
- 2 - A 16 OR2 ! 0 4 0 5 :175
- 3 - A 16 OR2 s 0 3 0 5 ~222~1
- 7 - A 16 AND2 s 0 2 0 3 ~226~1
- 7 - A 21 DFFE + 0 3 1 2 :247
- 1 - A 21 DFFE + 0 3 1 3 :248
- 3 - A 21 DFFE + 0 3 1 5 :249
- 5 - A 21 DFFE + 0 2 1 5 :250
- 1 - A 16 DFFE + 0 3 1 3 :251
- 8 - A 16 DFFE + 0 2 1 5 :252
- 6 - A 16 DFFE + 0 2 1 4 :253
- 1 - A 14 DFFE + 0 1 1 5 :254
- 6 - A 22 OR2 s 0 4 0 2 ~277~1
- 3 - A 24 OR2 s 0 2 0 1 ~277~2
- 4 - A 14 OR2 s 0 4 0 1 ~277~3
- 2 - A 14 OR2 s 0 4 0 1 ~277~4
- 5 - A 22 OR2 s 0 2 0 1 ~277~5
- 7 - A 22 OR2 s 0 4 0 1 ~277~6
- 4 - A 04 AND2 ! 3 1 0 2 :298
- 2 - A 17 AND2 s 2 0 0 2 ~329~1
- 6 - A 18 OR2 s 2 2 0 1 ~329~2
- 6 - A 14 OR2 s 2 2 0 1 ~329~3
- 4 - A 24 OR2 s 2 2 0 1 ~329~4
- 8 - A 21 OR2 s 2 2 0 1 ~329~5
- 2 - A 21 OR2 s 1 3 0 1 ~329~6
- 7 - A 18 OR2 s 2 2 0 1 ~329~7
- 1 - A 18 AND2 s 0 4 0 1 ~329~8
- 3 - A 14 OR2 s 3 1 0 1 ~329~9
- 1 - A 22 OR2 s 2 2 0 1 ~329~10
- 2 - A 22 OR2 s 2 2 0 1 ~329~11
- 8 - A 17 OR2 s 2 2 0 1 ~329~12
- 4 - A 22 AND2 s 0 4 0 1 ~329~13
- 8 - A 22 DFFE + 0 4 0 1 alarm1 (:333)
- 6 - A 17 OR2 3 1 0 1 :351
- 1 - A 04 OR2 4 0 0 1 :363
- 5 - A 17 AND2 s 4 0 0 1 ~388~1
- 1 - A 17 AND2 s 4 0 0 1 ~389~1
- 4 - A 17 AND2 s 1 3 0 1 ~389~2
- 3 - A 17 OR2 3 1 0 1 :394
- 2 - A 04 OR2 3 1 0 1 :406
- 3 - A 04 OR2 2 0 0 2 :424
- 2 - A 18 DFFE + 0 1 0 1 sound1 (:442)
- 3 - A 18 DFFE + 0 0 0 2 sound0 (:443)
- 4 - A 18 DFFE + 0 2 1 1 :447
- 5 - A 18 AND2 s 4 0 0 1 ~455~1
- 8 - A 18 OR2 s 1 3 0 1 ~455~2
- 7 - A 17 DFFE + 0 4 1 1 :459
- 3 - A 22 OR2 1 2 1 0 :461
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\amj\eda\experiment\calendar_clock\alarm.rpt
alarm
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 23/ 96( 23%) 5/ 48( 10%) 31/ 48( 64%) 3/16( 18%) 6/16( 37%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 4/ 48( 8%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
C: 3/ 96( 3%) 0/ 48( 0%) 5/ 48( 10%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 4/24( 16%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 3/24( 12%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\amj\eda\experiment\calendar_clock\alarm.rpt
alarm
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 set_ahr
INPUT 8 set_amin
INPUT 6 clk_4Hz
Device-Specific Information: e:\amj\eda\experiment\calendar_clock\alarm.rpt
alarm
** EQUATIONS **
clk_1KHz : INPUT;
clk_4Hz : INPUT;
disp_mode0 : INPUT;
disp_mode1 : INPUT;
hour0 : INPUT;
hour1 : INPUT;
hour2 : INPUT;
hour3 : INPUT;
hour4 : INPUT;
hour5 : INPUT;
hour6 : INPUT;
hour7 : INPUT;
min0 : INPUT;
min1 : INPUT;
min2 : INPUT;
min3 : INPUT;
min4 : INPUT;
min5 : INPUT;
min6 : INPUT;
min7 : INPUT;
sec0 : INPUT;
sec1 : INPUT;
sec2 : INPUT;
sec3 : INPUT;
sec4 : INPUT;
sec5 : INPUT;
sec6 : INPUT;
sec7 : INPUT;
set : INPUT;
set_ahr : INPUT;
set_amin : INPUT;
-- Node name is 'ahour0'
-- Equation name is 'ahour0', type is output
ahour0 = _LC1_A14;
-- Node name is 'ahour1'
-- Equation name is 'ahour1', type is output
ahour1 = _LC6_A16;
-- Node name is 'ahour2'
-- Equation name is 'ahour2', type is output
ahour2 = _LC8_A16;
-- Node name is 'ahour3'
-- Equation name is 'ahour3', type is output
ahour3 = _LC1_A16;
-- Node name is 'ahour4'
-- Equation name is 'ahour4', type is output
ahour4 = _LC5_A21;
-- Node name is 'ahour5'
-- Equation name is 'ahour5', type is output
ahour5 = _LC3_A21;
-- Node name is 'ahour6'
-- Equation name is 'ahour6', type is output
ahour6 = _LC1_A21;
-- Node name is 'ahour7'
-- Equation name is 'ahour7', type is output
ahour7 = _LC7_A21;
-- Node name is 'alarm'
-- Equation name is 'alarm', type is output
alarm = _LC3_A22;
-- Node name is ':333' = 'alarm1'
-- Equation name is 'alarm1', location is LC8_A22, type is buried.
alarm1 = DFFE( _EQ001, GLOBAL( clk_4Hz), VCC, VCC, VCC);
_EQ001 = _LC1_A18 & _LC2_A14 & _LC4_A22
# _LC1_A18 & _LC4_A22 & _LC7_A22;
-- Node name is 'alarm2'
-- Equation name is 'alarm2', type is output
alarm2 = _LC7_A17;
-- Node name is 'amin0'
-- Equation name is 'amin0', type is output
amin0 = _LC8_A14;
-- Node name is 'amin1'
-- Equation name is 'amin1', type is output
amin1 = _LC2_A24;
-- Node name is 'amin2'
-- Equation name is 'amin2', type is output
amin2 = _LC7_A24;
-- Node name is 'amin3'
-- Equation name is 'amin3', type is output
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