📄 clkdiv1000.rpt
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Device-Specific Information:e:\amj\eda\experiment\calendar_clock\clkdiv1000.rpt
clkdiv1000
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC31 clkout
| +----------------------------- LC22 count2
| | +--------------------------- LC21 count3
| | | +------------------------- LC20 count4
| | | | +----------------------- LC18 count5
| | | | | +--------------------- LC24 count6
| | | | | | +------------------- LC23 count7
| | | | | | | +----------------- LC17 count8
| | | | | | | | +--------------- LC19 count9
| | | | | | | | | +------------- LC27 |lpm_add_sub:62|addcore:adder|addcore:adder0|result_node3
| | | | | | | | | | +----------- LC25 |lpm_add_sub:62|addcore:adder|addcore:adder0|result_node4
| | | | | | | | | | | +--------- LC26 |lpm_add_sub:62|addcore:adder|addcore:adder0|result_node5
| | | | | | | | | | | | +------- LC28 |lpm_add_sub:62|addcore:adder|addcore:adder0|result_node6
| | | | | | | | | | | | | +----- LC29 |lpm_add_sub:62|addcore:adder|addcore:adder0|result_node7
| | | | | | | | | | | | | | +--- LC30 |lpm_add_sub:62|addcore:adder|addcore:adder1|result_node0
| | | | | | | | | | | | | | | +- LC32 |lpm_add_sub:62|addcore:adder|addcore:adder1|result_node1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC22 -> * * * * * * * * * * * * * * * * | - * | <-- count2
LC21 -> * - * * * * * * * * * * * * * * | - * | <-- count3
LC20 -> * - * * * * * * * - * * * * * * | - * | <-- count4
LC18 -> * - * * * * * * * - - * * * * * | - * | <-- count5
LC24 -> * - * * * * * * * - - - * * * * | - * | <-- count6
LC23 -> * - * * * * * * * - - - - * * * | - * | <-- count7
LC17 -> * - * * * * * * * - - - - - * * | - * | <-- count8
LC19 -> * - * * * * * * * - - - - - - * | - * | <-- count9
LC27 -> - - * - - - - - - - - - - - - - | - * | <-- |lpm_add_sub:62|addcore:adder|addcore:adder0|result_node3
LC25 -> - - - * - - - - - - - - - - - - | - * | <-- |lpm_add_sub:62|addcore:adder|addcore:adder0|result_node4
LC26 -> - - - - * - - - - - - - - - - - | - * | <-- |lpm_add_sub:62|addcore:adder|addcore:adder0|result_node5
LC28 -> - - - - - * - - - - - - - - - - | - * | <-- |lpm_add_sub:62|addcore:adder|addcore:adder0|result_node6
LC29 -> - - - - - - * - - - - - - - - - | - * | <-- |lpm_add_sub:62|addcore:adder|addcore:adder0|result_node7
LC30 -> - - - - - - - * - - - - - - - - | - * | <-- |lpm_add_sub:62|addcore:adder|addcore:adder1|result_node0
LC32 -> - - - - - - - - * - - - - - - - | - * | <-- |lpm_add_sub:62|addcore:adder|addcore:adder1|result_node1
Pin
43 -> - - - - - - - - - - - - - - - - | - - | <-- clkin
LC1 -> * * * * * * * * * * * * * * * * | * * | <-- count0
LC4 -> * * * * * * * * * * * * * * * * | - * | <-- count1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information:e:\amj\eda\experiment\calendar_clock\clkdiv1000.rpt
clkdiv1000
** EQUATIONS **
clkin : INPUT;
-- Node name is 'clkout' = ':61'
-- Equation name is 'clkout', type is output
clkout = DFFE( _EQ001 $ GND, GLOBAL( clkin), VCC, VCC, VCC);
_EQ001 = count0 & count1 & count2 & !count3 & !count4 & count5 &
count6 & count7 & count8 & count9;
-- Node name is 'count0' = ':57'
-- Equation name is 'count0', type is output
count0 = TFFE( VCC, GLOBAL( clkin), VCC, VCC, VCC);
-- Node name is 'count1' = ':56'
-- Equation name is 'count1', type is output
count1 = TFFE( count0, GLOBAL( clkin), VCC, VCC, VCC);
-- Node name is 'count2' = ':55'
-- Equation name is 'count2', type is output
count2 = TFFE( _EQ002, GLOBAL( clkin), VCC, VCC, VCC);
_EQ002 = count0 & count1;
-- Node name is 'count3' = ':54'
-- Equation name is 'count3', type is output
count3 = DFFE( _EQ003 $ _LC027, GLOBAL( clkin), VCC, VCC, VCC);
_EQ003 = count0 & count1 & count2 & !count3 & !count4 & count5 &
count6 & count7 & count8 & count9 & _LC027;
-- Node name is 'count4' = ':53'
-- Equation name is 'count4', type is output
count4 = DFFE( _EQ004 $ _LC025, GLOBAL( clkin), VCC, VCC, VCC);
_EQ004 = count0 & count1 & count2 & !count3 & !count4 & count5 &
count6 & count7 & count8 & count9 & _LC025;
-- Node name is 'count5' = ':52'
-- Equation name is 'count5', type is output
count5 = DFFE( _EQ005 $ _LC026, GLOBAL( clkin), VCC, VCC, VCC);
_EQ005 = count0 & count1 & count2 & !count3 & !count4 & count5 &
count6 & count7 & count8 & count9 & _LC026;
-- Node name is 'count6' = ':51'
-- Equation name is 'count6', type is output
count6 = DFFE( _EQ006 $ _LC028, GLOBAL( clkin), VCC, VCC, VCC);
_EQ006 = count0 & count1 & count2 & !count3 & !count4 & count5 &
count6 & count7 & count8 & count9 & _LC028;
-- Node name is 'count7' = ':50'
-- Equation name is 'count7', type is output
count7 = DFFE( _EQ007 $ _LC029, GLOBAL( clkin), VCC, VCC, VCC);
_EQ007 = count0 & count1 & count2 & !count3 & !count4 & count5 &
count6 & count7 & count8 & count9 & _LC029;
-- Node name is 'count8' = ':49'
-- Equation name is 'count8', type is output
count8 = DFFE( _EQ008 $ _LC030, GLOBAL( clkin), VCC, VCC, VCC);
_EQ008 = count0 & count1 & count2 & !count3 & !count4 & count5 &
count6 & count7 & count8 & count9 & _LC030;
-- Node name is 'count9' = ':48'
-- Equation name is 'count9', type is output
count9 = DFFE( _EQ009 $ _LC032, GLOBAL( clkin), VCC, VCC, VCC);
_EQ009 = count0 & count1 & count2 & !count3 & !count4 & count5 &
count6 & count7 & count8 & count9 & _LC032;
-- Node name is '|lpm_add_sub:62|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC027', type is buried
_LC027 = LCELL( count3 $ _EQ010);
_EQ010 = count0 & count1 & count2;
-- Node name is '|lpm_add_sub:62|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC025', type is buried
_LC025 = LCELL( count4 $ _EQ011);
_EQ011 = count0 & count1 & count2 & count3;
-- Node name is '|lpm_add_sub:62|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC026', type is buried
_LC026 = LCELL( count5 $ _EQ012);
_EQ012 = count0 & count1 & count2 & count3 & count4;
-- Node name is '|lpm_add_sub:62|addcore:adder|addcore:adder0|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC028', type is buried
_LC028 = LCELL( count6 $ _EQ013);
_EQ013 = count0 & count1 & count2 & count3 & count4 & count5;
-- Node name is '|lpm_add_sub:62|addcore:adder|addcore:adder0|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC029', type is buried
_LC029 = LCELL( count7 $ _EQ014);
_EQ014 = count0 & count1 & count2 & count3 & count4 & count5 &
count6;
-- Node name is '|lpm_add_sub:62|addcore:adder|addcore:adder1|result_node0' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC030', type is buried
_LC030 = LCELL( count8 $ _EQ015);
_EQ015 = count0 & count1 & count2 & count3 & count4 & count5 &
count6 & count7;
-- Node name is '|lpm_add_sub:62|addcore:adder|addcore:adder1|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC032', type is buried
_LC032 = LCELL( count9 $ _EQ016);
_EQ016 = count0 & count1 & count2 & count3 & count4 & count5 &
count6 & count7 & count8;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\amj\eda\experiment\calendar_clock\clkdiv1000.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,766K
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