clk_divide_3.map.eqn

VHDL语言编写三分频

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--temp1 is temp1
--operation mode is normal

temp1_lut_out = temp1 $ (!rst & (counter1[1]));
temp1 = DFFEAS(temp1_lut_out, clkin, VCC, , , , , , );


--temp2 is temp2
--operation mode is normal

temp2_lut_out = temp2 $ (!rst & (counter2[1]));
temp2 = DFFEAS(temp2_lut_out, !clkin, VCC, , , , , , );


--A1L3 is clkout~0
--operation mode is normal

A1L3 = temp1 & temp2;


--counter1[1] is counter1[1]
--operation mode is normal

counter1[1]_lut_out = counter1[1] $ (!rst & (counter1[0]));
counter1[1] = DFFEAS(counter1[1]_lut_out, clkin, VCC, , , , , , );


--counter2[1] is counter2[1]
--operation mode is normal

counter2[1]_lut_out = counter2[1] $ (!rst & (counter2[0]));
counter2[1] = DFFEAS(counter2[1]_lut_out, !clkin, VCC, , , , , , );


--counter1[0] is counter1[0]
--operation mode is normal

counter1[0]_lut_out = !counter1[0];
counter1[0] = DFFEAS(counter1[0]_lut_out, clkin, VCC, , !rst, , , , );


--counter2[0] is counter2[0]
--operation mode is normal

counter2[0]_lut_out = !counter2[0];
counter2[0] = DFFEAS(counter2[0]_lut_out, !clkin, VCC, , !rst, , , , );


--rst is rst
--operation mode is input

rst = INPUT();


--clkin is clkin
--operation mode is input

clkin = INPUT();


--clkout is clkout
--operation mode is output

clkout = OUTPUT(A1L3);


--t1 is t1
--operation mode is output

t1 = OUTPUT(temp1);


--t2 is t2
--operation mode is output

t2 = OUTPUT(temp2);