clk_divide_3.map.summary

VHDL语言编写三分频

Analysis & Synthesis Status : Successful - Fri Mar 17 00:48:10 2006
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : clk_divide_3
Top-level Entity Name : clk_divide_3
Family : Cyclone
Total logic elements : 7
Total pins : 5
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0