clk_divide_3.fit.summary

VHDL语言编写三分频

Fitter Status : Successful - Fri Mar 17 00:48:20 2006
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : clk_divide_3
Top-level Entity Name : clk_divide_3
Family : Cyclone
Device : EP1C12F324C8
Timing Models : Final
Total logic elements : 7 / 12,060 ( < 1 % )
Total pins : 5 / 249 ( 2 % )
Total virtual pins : 0
Total memory bits : 0 / 239,616 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )