tiaoping.vhd

条屏控制器的CPLD编程,主要完成移位寄存器、编码器和译码器的功能

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity tiaoping is
	port( 
	       p1_5,p1_6:in std_logic;  
	   p1_3,p1_4,clk:in std_logic;
         rd,wr,d_sel:in std_logic;
		         din:in std_logic_vector(7 downto 0);
 sel_addr0,sel_addr1:in std_logic;    
            cpld_sel:in std_logic;        
 serial_or,serial_og:out std_logic;          		  
		  addr_out0,addr_out1,addr_out2,
		   addr_out3:out std_logic; 
	         sel_out0,sel_out1,sel_out2,
	        sel_out3:out std_logic;
	         clk_out:out std_logic;
	     xlat,oe_out:out std_logic);
end tiaoping;

architecture behav of tiaoping is 
		signal temp:std_logic_vector(7 downto 0);
		signal addr_count:std_logic_vector(3 downto 0);
		signal flag_init:std_logic;
		signal flag_low:std_logic;
		signal flag_data:std_logic;
		signal flag_counter:std_logic;
begin
	process(cpld_sel,wr,p1_6)
	begin
		if (cpld_sel='1' ) then
			if (p1_6='0') then
				temp<="00000000";
				flag_counter<='0';
			elsif (wr'event) and (wr='1') then
				temp<=din;
				flag_counter<='1';
			end if;
		end if;
	end process;
	
	process(cpld_sel,wr,clk,d_sel,p1_6,flag_counter)
		variable counter:integer range 0 to 10:=10; 
		variable data_count:integer range 0 to 10:=10;
	begin	
		if (p1_6='0') then
			if (cpld_sel='1')then
				data_count:=0;
				counter:=8;
				clk_out<='0';
				flag_init<='0';
				flag_data<='0';
				flag_low<='1';
				serial_or<='1';
				serial_og<='1';
			end if;
		elsif (clk'event) and (clk='1') and (wr='1') and (flag_counter='1')then
				if (data_count<9) then
					if (flag_low='1') then
						if (flag_init='0') then
							flag_init<='1';
							counter:=counter-1;
							if (d_sel='1') then
		        				serial_or<= not temp(counter);
							else
								serial_og<= not temp(counter);
							end if;
						    data_count:=data_count+1;
						end if;
						clk_out<='0';
						flag_low<='0';
						flag_data<='1';	
					elsif (flag_data='1') then
						counter:=counter-1;
						if (counter>=0) then
							if (d_sel='1') then
		        				serial_or<= not temp(counter);
							else
								serial_og<= not temp(counter);
							end if;
						end if;
						clk_out<='1';
						flag_data<='0';
						data_count:=data_count+1;
						flag_low<='1';
					end if;		
				end if;
		end if;
	end process;
			
	process(p1_3,cpld_sel,p1_5)
	begin
		if (cpld_sel='1') then
			if (p1_5='0') then
				addr_count<="0000";
	  		elsif (p1_3'event) and (p1_3='1') then
				addr_out0<=addr_count(0) after 20 ns; 
          		addr_out1<=addr_count(1) after 20 ns;
		   		addr_out2<=addr_count(2) after 20 ns;
		   		addr_out3<=addr_count(3) after 20 ns;
				addr_count<=addr_count+1;
			end if;	
		end if;
	end process;	
 	 	
	sel_out0 <= '1' when (sel_addr0 = '0') and (sel_addr1 = '0') and (cpld_sel = '0') else '0';
	sel_out1 <= '0' when (sel_addr0 = '1') and (sel_addr1 = '0') and (cpld_sel = '0') else '1';
	sel_out2 <= '0' when (sel_addr0 = '0') and (sel_addr1 = '1') and (cpld_sel = '0') and (rd='0') else '1';
	sel_out3 <= '0' when (sel_addr0 = '1') and (sel_addr1 = '1') and (cpld_sel = '0') else '1';
	
	oe_out <=  p1_4;
	xlat <=  p1_3;
	
end behav;