📄 tiaoping.sim.vwf

📁 条屏控制器的CPLD编程,主要完成移位寄存器、编码器和译码器的功能
💻 VWF
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/

/*
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.
*/

HEADER
{
	VERSION = 1;
	TIME_UNIT = ns;
	PRINT_OPTIONS = "Print_options_version 6\
range_start 0ps\
range_end 10.0ms\
width 1\
names_percentage 25\
comments 1\
grid_lines 1\
time_bars 1\
name_every_page 0\
expand_groups 0\
print_all 1";
	SIMULATION_TIME = 800000.0;
	GRID_PHASE = 0.0;
	GRID_PERIOD = 0.0;
	GRID_DUTY_CYCLE = 50;
}

SIGNAL("wr")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("d_sel")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("cpld_sel")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("clk")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("serial_or")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("serial_og")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("clk_out")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("din[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("din[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("din[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("din[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("din[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("din[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("din[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("din[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("temp")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 8;
	LSB_INDEX = 0;
	DIRECTION = REGISTERED;
	PARENT = "";
}

SIGNAL("temp[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "temp";
}

SIGNAL("temp[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "temp";
}

SIGNAL("temp[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "temp";
}

SIGNAL("temp[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "temp";
}

SIGNAL("temp[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "temp";
}

SIGNAL("temp[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "temp";
}

SIGNAL("temp[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "temp";
}

SIGNAL("temp[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "temp";
}

SIGNAL("p1_6")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("counter")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 3;
	LSB_INDEX = 0;
	DIRECTION = REGISTERED;
	PARENT = "";
}

SIGNAL("counter[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "counter";
}

SIGNAL("counter[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "counter";
}

SIGNAL("counter[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "counter";
}

SIGNAL("p1_3")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

GROUP("din")
{
	MEMBERS = "din[7]", "din[6]", "din[5]", "din[4]", "din[3]", "din[2]", "din[1]", "din[0]";
}

SIGNAL("xlat")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("oe_out")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("sel_out0")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("sel_out2")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("sel_out1")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("sel_out3")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("addr_out0")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("addr_out1")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("addr_out2")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("addr_out3")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

TRANSITION_LIST("wr")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 54.4;
		LEVEL 0 FOR 452.094;
		LEVEL 1 FOR 77236.651;
		LEVEL 0 FOR 490.618;
		LEVEL 1 FOR 77760.392;
		LEVEL 0 FOR 483.417;
		LEVEL 1 FOR 77086.53;
		LEVEL 0 FOR 483.417;
		LEVEL 1 FOR 77952.481;
		LEVEL 0 FOR 546.759;
		LEVEL 1 FOR 77092.336;
		LEVEL 0 FOR 598.822;
		LEVEL 1 FOR 77548.328;
		LEVEL 0 FOR 483.417;
		LEVEL 1 FOR 76988.405;
		LEVEL 0 FOR 483.417;
		LEVEL 1 FOR 78258.516;
		LEVEL 0 FOR 690.94;
		LEVEL 1 FOR 77063.441;
		LEVEL 0 FOR 483.417;
		LEVEL 1 FOR 77762.202;
		LEVEL 0 FOR 633.141;
		LEVEL 1 FOR 19366.859;
	}
}

TRANSITION_LIST("d_sel")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 800000.0;
	}
}

TRANSITION_LIST("cpld_sel")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 800000.0;
	}
}

TRANSITION_LIST("clk")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 750.0;
		LEVEL 1 FOR 250.0;
		NODE
		{
			REPEAT = 153;
			LEVEL 0 FOR 250.0;
			LEVEL 1 FOR 250.0;
		}
		LEVEL 0 FOR 1250.0;
		LEVEL 1 FOR 250.0;
		NODE
		{
			REPEAT = 153;
			LEVEL 0 FOR 250.0;
			LEVEL 1 FOR 250.0;
		}
		LEVEL 0 FOR 1250.0;
		LEVEL 1 FOR 250.0;
		NODE
		{
			REPEAT = 153;
			LEVEL 0 FOR 250.0;
			LEVEL 1 FOR 250.0;
		}
		LEVEL 0 FOR 750.0;
		LEVEL 1 FOR 250.0;
		NODE
		{
			REPEAT = 155;
			LEVEL 0 FOR 250.0;
			LEVEL 1 FOR 250.0;
		}
		LEVEL 0 FOR 750.0;
		LEVEL 1 FOR 250.0;
		NODE
		{
			REPEAT = 153;
			LEVEL 0 FOR 250.0;
			LEVEL 1 FOR 250.0;
		}
		LEVEL 0 FOR 750.0;
		LEVEL 1 FOR 250.0;
		NODE
		{
			REPEAT = 154;
			LEVEL 0 FOR 250.0;
			LEVEL 1 FOR 250.0;
		}
		LEVEL 0 FOR 750.0;
		LEVEL 1 FOR 250.0;
		NODE
		{
			REPEAT = 153;
			LEVEL 0 FOR 250.0;
			LEVEL 1 FOR 250.0;
		}
		LEVEL 0 FOR 750.0;
		LEVEL 1 FOR 250.0;
		NODE
		{
			REPEAT = 155;
			LEVEL 0 FOR 250.0;
			LEVEL 1 FOR 250.0;
		}
		LEVEL 0 FOR 1250.0;
		LEVEL 1 FOR 250.0;
		NODE
		{
			REPEAT = 153;
			LEVEL 0 FOR 250.0;
			LEVEL 1 FOR 250.0;
		}
		LEVEL 0 FOR 1250.0;
		LEVEL 1 FOR 250.0;
		NODE
		{
			REPEAT = 153;
			LEVEL 0 FOR 250.0;
			LEVEL 1 FOR 250.0;
		}
		LEVEL 0 FOR 1250.0;
		LEVEL 1 FOR 250.0;
		NODE
		{
			REPEAT = 38;
			LEVEL 0 FOR 250.0;
			LEVEL 1 FOR 250.0;
		}
	}
}

TRANSITION_LIST("serial_or")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 10.762;
		LEVEL 1 FOR 746.238;
		LEVEL 0 FOR 500.0;
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 1000.0;
			LEVEL 0 FOR 1000.0;
		}
		LEVEL 1 FOR 1000.0;
		LEVEL 0 FOR 69749.623;
		LEVEL 1 FOR 2750.377;
		LEVEL 0 FOR 500.0;
		NODE
		{
			REPEAT = 3;
			LEVEL 1 FOR 1000.0;
			LEVEL 0 FOR 1000.0;
		}
		LEVEL 1 FOR 1000.0;
		LEVEL 0 FOR 68484.742;
		LEVEL 1 FOR 2015.258;
		LEVEL 0 FOR 75521.945;
		LEVEL 1 FOR 80478.055;
		LEVEL 0 FOR 75749.623;
		LEVEL 1 FOR 2250.377;
		LEVEL 0 FOR 75963.909;
		LEVEL 1 FOR 2036.091;
		LEVEL 0 FOR 75054.683;
		LEVEL 1 FOR 2445.317;
		LEVEL 0 FOR 76126.111;
		LEVEL 1 FOR 2373.889;
		LEVEL 0 FOR 75535.338;
		LEVEL 1 FOR 2464.662;
		LEVEL 0 FOR 75786.826;
		LEVEL 1 FOR 2213.174;
		LEVEL 0 FOR 19243.0;
	}
}

TRANSITION_LIST("serial_og")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 10.762;
		LEVEL 1 FOR 799989.238;
	}
}

TRANSITION_LIST("clk_out")
{
	NODE
	{
12 3 下一页
💿 文件大小 402 K
👤 上传用户 fairbank
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

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