📄 tiaoping_old.vhd
字号:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity tiaoping is
port(
tdi,tms,tdo,tck:in std_logic;
p1_5,p1_6:in std_logic;
p1_3,p1_4,clk:in std_logic;
rd,wr,d_sel:in std_logic;
din:in std_logic_vector(7 downto 0);
sel_addr0,sel_addr1:in std_logic;
cpld_sel:in std_logic;
serial_or,serial_og:out std_logic;
addr_out0,addr_out1,addr_out2,
addr_out3:out std_logic;
sel_out0,sel_out1,sel_out2,
sel_out3:out std_logic;
clk_out:out std_logic;
xlat,oe_out:out std_logic
);
end tiaoping;
architecture behav of tiaoping is
signal tmp8:std_logic_vector(7 downto 0);
signal count_x:std_logic_vector(3 downto 0);
signal count_f:std_logic_vector(3 downto 0);
begin
process(cpld_sel,wr,clk,d_sel)
begin
if (clk'event) and (clk='1') then
if (cpld_sel='1') then
if (wr='0') then
tmp8<=din;
elsif (wr='1') then
if (d_sel='1') then
serial_or<=tmp8(7);
for i in tmp8'high downto tmp8'low+1 loop
tmp8(i)<=tmp8(i-1);
end loop;
tmp8(tmp8'low)<='0';
else
serial_og<=tmp8(7);
for i in tmp8'high downto tmp8'low+1 loop
tmp8(i)<=tmp8(i-1);
end loop;
tmp8(tmp8'low)<='0';
end if;
end if;
if (p1_6='0') then
tmp8<="00000000";
serial_or<=tmp8(7);
serial_og<=tmp8(7);
end if;
else
tmp8<="00000000";
serial_or<=tmp8(7);
serial_og<=tmp8(7);
end if;
end if;
end process;
process(clk,p1_6)
begin
if(clk'event and clk='1')then
if (count_f="0001") then
clk_out<='1';
count_f<=count_f+1;
elsif (count_f="0011") then
clk_out<='0';
count_f<="0000";
else
count_f<=count_f+1;
end if;
end if;
end process;
process(p1_3)
begin
if (p1_3'event) and (p1_3='0') then
addr_out0<=count_x(0) after 20 ns;
addr_out1<=count_x(1) after 20 ns;
addr_out2<=count_x(2) after 20 ns;
addr_out3<=count_x(3) after 20 ns;
if (count_x="1111") then
count_x<="0000";
end if;
count_x<=count_x+1;
end if;
end process;
--process(p1_6)
--begin
--if (p1_6'event) and (p1_6='0') then
--if (cpld_sel='1') then
--count_f<="0000";
--count_x<="0000";
--tmp8<="00000000";
--end if;
--end if;
--end process;
sel_out0 <= '1' when (sel_addr0 = '0') and (sel_addr1 = '0') and (cpld_sel = '0') else '0';
sel_out1 <= '0' when (sel_addr0 = '1') and (sel_addr1 = '0') and (cpld_sel = '0') and ((wr = '0') or (rd = '0')) else '1';
sel_out2 <= '0' when (sel_addr0 = '0') and (sel_addr1 = '1') and (cpld_sel = '0') and (rd = '0') else '1';
sel_out3 <= '0' when (sel_addr0 = '1') and (sel_addr1 = '1') and (cpld_sel = '0') and ((wr = '0') or (rd = '0')) else '1';
oe_out <= p1_4;
xlat <= p1_3;
end behav;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -