maxplusii_to_quartus_name_mapping.txt

条屏控制器的CPLD编程,主要完成移位寄存器、编码器和译码器的功能

 -- Copyright (C) 1991-2004 Altera Corporation
 -- Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
 -- support information,  device programming or simulation file,  and any other
 -- associated  documentation or information  provided by  Altera  or a partner
 -- under  Altera's   Megafunction   Partnership   Program  may  be  used  only
 -- to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
 -- other  use  of such  megafunction  design,  netlist,  support  information,
 -- device programming or simulation file,  or any other  related documentation
 -- or information  is prohibited  for  any  other purpose,  including, but not
 -- limited to  modification,  reverse engineering,  de-compiling, or use  with
 -- any other  silicon devices,  unless such use is  explicitly  licensed under
 -- a separate agreement with  Altera  or a megafunction partner.  Title to the
 -- intellectual property,  including patents,  copyrights,  trademarks,  trade
 -- secrets,  or maskworks,  embodied in any such megafunction design, netlist,
 -- support  information,  device programming or simulation file,  or any other
 -- related documentation or information provided by  Altera  or a megafunction
 -- partner, remains with Altera, the megafunction partner, or their respective
 -- licensors. No other licenses, including any licenses needed under any third
 -- party's intellectual property, are provided herein.

 -- VERSION "Version 5.0 Build 148 04/26/2005 SJ Full Version"
 -- DATE "02/20/2006 14:14:28"

Conversion results for tiaoping
+-----------------------+----------------------+
| MAX+PLUS II node name | Quartus II node name |
+-----------------------+----------------------+
| |addr_out0            | addr_out[0]          |
| |addr_out1            | addr_out[1]          |
| |addr_out2            | addr_out[2]          |
| |addr_out3            | addr_out[3]          |
| |din0                 | din[0]               |
| |din1                 | din[1]               |
| |din2                 | din[2]               |
| |din3                 | din[3]               |
| |din4                 | din[4]               |
| |din5                 | din[5]               |
| |din6                 | din[6]               |
| |din7                 | din[7]               |
| |p1_3                 | p[1][3]              |
| |p1_4                 | p[1][4]              |
| |p1_5                 | p[1][5]              |
| |p1_6                 | p[1][6]              |
| |sel_addr0            | sel_addr[0]          |
| |sel_addr1            | sel_addr[1]          |
| |sel_out0             | sel_out[0]           |
| |sel_out1             | sel_out[1]           |
| |sel_out2             | sel_out[2]           |
| |sel_out3             | sel_out[3]           |
+-----------------------+----------------------+