📄 or1200_defines.v
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////////////////////////////////////////////////////////////////////////// //////// OR1200's definitions //////// //////// This file is part of the OpenRISC 1200 project //////// http://www.opencores.org/cores/or1k/ //////// //////// Description //////// Parameters of the OR1200 core //////// //////// To Do: //////// - add parameters that are missing //////// //////// Author(s): //////// - Damjan Lampret, lampret@opencores.org //////// ////////////////////////////////////////////////////////////////////////////// //////// Copyright (C) 2000 Authors and OPENCORES.ORG //////// //////// This source file may be used and distributed without //////// restriction provided that this copyright statement is not //////// removed from the file and that any derivative work contains //////// the original copyright notice and the associated disclaimer. //////// //////// This source file is free software; you can redistribute it //////// and/or modify it under the terms of the GNU Lesser General //////// Public License as published by the Free Software Foundation; //////// either version 2.1 of the License, or (at your option) any //////// later version. //////// //////// This source is distributed in the hope that it will be //////// useful, but WITHOUT ANY WARRANTY; without even the implied //////// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //////// PURPOSE. See the GNU Lesser General Public License for more //////// details. //////// //////// You should have received a copy of the GNU Lesser General //////// Public License along with this source; if not, download it //////// from http://www.opencores.org/lgpl.shtml //////// ////////////////////////////////////////////////////////////////////////////// CVS Revision History//// $Log: or1200_defines.v,v $// Revision 1.35 2003/04/24 00:16:07 lampret// No functional changes. Added defines to disable implementation of multiplier/MAC//// Revision 1.34 2003/04/20 22:23:57 lampret// No functional change. Only added customization for exception vectors.//// Revision 1.33 2003/04/07 20:56:07 lampret// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description.//// Revision 1.32 2003/04/07 01:26:57 lampret// RFRAM defines comments updated. Altera LPM option added.//// Revision 1.31 2002/12/08 08:57:56 lampret// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.//// Revision 1.30 2002/10/28 15:09:22 mohor// Previous check-in was done by mistake.//// Revision 1.29 2002/10/28 15:03:50 mohor// Signal scanb_sen renamed to scanb_en.//// Revision 1.28 2002/10/17 20:04:40 lampret// Added BIST scan. Special VS RAMs need to be used to implement BIST.//// Revision 1.27 2002/09/16 03:13:23 lampret// Removed obsolete comment.//// Revision 1.26 2002/09/08 05:52:16 lampret// Added optional l.div/l.divu insns. By default they are disabled.//// Revision 1.25 2002/09/07 19:16:10 lampret// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].//// Revision 1.24 2002/09/07 05:42:02 lampret// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.//// Revision 1.23 2002/09/04 00:50:34 lampret// Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v.//// Revision 1.22 2002/09/03 22:28:21 lampret// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.//// Revision 1.21 2002/08/22 02:18:55 lampret// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.//// Revision 1.20 2002/08/18 21:59:45 lampret// Disable SB until it is tested//// Revision 1.19 2002/08/18 19:53:08 lampret// Added store buffer.//// Revision 1.18 2002/08/15 06:04:11 lampret// Fixed Xilinx trace buffer address. REported by Taylor Su.//// Revision 1.17 2002/08/12 05:31:44 lampret// Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section.//// Revision 1.16 2002/07/14 22:17:17 lampret// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.//// Revision 1.15 2002/06/08 16:20:21 lampret// Added defines for enabling generic FF based memory macro for register file.//// Revision 1.14 2002/03/29 16:24:06 lampret// Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives//// Revision 1.13 2002/03/29 15:16:55 lampret// Some of the warnings fixed.//// Revision 1.12 2002/03/28 19:25:42 lampret// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.//// Revision 1.11 2002/03/28 19:13:17 lampret// Updated defines.//// Revision 1.10 2002/03/14 00:30:24 lampret// Added alternative for critical path in DU.//// Revision 1.9 2002/03/11 01:26:26 lampret// Fixed async loop. Changed multiplier type for ASIC.//// Revision 1.8 2002/02/11 04:33:17 lampret// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.//// Revision 1.7 2002/02/01 19:56:54 lampret// Fixed combinational loops.//// Revision 1.6 2002/01/19 14:10:22 lampret// Fixed OR1200_XILINX_RAM32X1D.//// Revision 1.5 2002/01/18 07:56:00 lampret// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.//// Revision 1.4 2002/01/14 09:44:12 lampret// Default ASIC configuration does not sample WB inputs.//// Revision 1.3 2002/01/08 00:51:08 lampret// Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be.//// Revision 1.2 2002/01/03 21:23:03 lampret// Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target.//// Revision 1.1 2002/01/03 08:16:15 lampret// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.//// Revision 1.20 2001/12/04 05:02:36 lampret// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32//// Revision 1.19 2001/11/27 19:46:57 lampret// Now FPGA and ASIC target are separate.//// Revision 1.18 2001/11/23 21:42:31 simons// Program counter divided to PPC and NPC.//// Revision 1.17 2001/11/23 08:38:51 lampret// Changed DSR/DRR behavior and exception detection.//// Revision 1.16 2001/11/20 21:30:38 lampret// Added OR1200_REGISTERED_INPUTS.//// Revision 1.15 2001/11/19 14:29:48 simons// Cashes disabled.//// Revision 1.14 2001/11/13 10:02:21 lampret// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)//// Revision 1.13 2001/11/12 01:45:40 lampret// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.//// Revision 1.12 2001/11/10 03:43:57 lampret// Fixed exceptions.//// Revision 1.11 2001/11/02 18:57:14 lampret// Modified virtual silicon instantiations.//// Revision 1.10 2001/10/21 17:57:16 lampret// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.//// Revision 1.9 2001/10/19 23:28:46 lampret// Fixed some synthesis warnings. Configured with caches and MMUs.//// Revision 1.8 2001/10/14 13:12:09 lampret// MP3 version.//// Revision 1.1.1.1 2001/10/06 10:18:36 igorm// no message//// Revision 1.3 2001/08/17 08:01:19 lampret// IC enable/disable.//// Revision 1.2 2001/08/13 03:36:20 lampret// Added cfg regs. Moved all defines into one defines.v file. More cleanup.//// Revision 1.1 2001/08/09 13:39:33 lampret// Major clean-up.//// Revision 1.2 2001/07/22 03:31:54 lampret// Fixed RAM's oen bug. Cache bypass under development.//// Revision 1.1 2001/07/20 00:46:03 lampret// Development version of RTL. Libraries are missing.//////// Dump VCD////`define OR1200_VCD_DUMP//// Generate debug messages during simulation////`define OR1200_VERBOSE// `define OR1200_ASIC//////////////////////////////////////////////////////////// Typical configuration for an ASIC//`ifdef OR1200_ASIC//// Target ASIC memories////`define OR1200_ARTISAN_SSP//`define OR1200_ARTISAN_SDP//`define OR1200_ARTISAN_STP`define OR1200_VIRTUALSILICON_SSP//`define OR1200_VIRTUALSILICON_STP_T1//`define OR1200_VIRTUALSILICON_STP_T2//// Do not implement Data cache////`define OR1200_NO_DC//// Do not implement Insn cache////`define OR1200_NO_IC//// Do not implement Data MMU////`define OR1200_NO_DMMU//// Do not implement Insn MMU////`define OR1200_NO_IMMU//// Select between ASIC optimized and generic multiplier////`define OR1200_ASIC_MULTP2_32X32`define OR1200_GENERIC_MULTP2_32X32//// Size/type of insn/data cache if implemented//// `define OR1200_IC_1W_4KB`define OR1200_IC_1W_8KB// `define OR1200_DC_1W_4KB`define OR1200_DC_1W_8KB`else///////////////////////////////////////////////////////////// Typical configuration for an FPGA////// Target FPGA memories////`define OR1200_ALTERA_LPM`define OR1200_XILINX_RAMB4//`define OR1200_XILINX_RAM32X1D//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D//// Do not implement Data cache////`define OR1200_NO_DC//// Do not implement Insn cache////`define OR1200_NO_IC//// Do not implement Data MMU////`define OR1200_NO_DMMU//// Do not implement Insn MMU////`define OR1200_NO_IMMU//// Select between ASIC and generic multiplier//// (Generic seems to trigger a bug in the Cadence Ncsim simulator)////`define OR1200_ASIC_MULTP2_32X32`define OR1200_GENERIC_MULTP2_32X32//// Size/type of insn/data cache if implemented// (consider available FPGA memory resources)//`define OR1200_IC_1W_4KB//`define OR1200_IC_1W_8KB`define OR1200_DC_1W_4KB//`define OR1200_DC_1W_8KB`endif////////////////////////////////////////////////////////////// Do not change below unless you know what you are doing////// Enable RAM BIST//// At the moment this only works for Virtual Silicon// single port RAMs. For other RAMs it has not effect.// Special wrapper for VS RAMs needs to be provided// with scan flops to facilitate bist scan.////`define OR1200_BIST//// Register OR1200 WISHBONE outputs// (must be defined/enabled)//`define OR1200_REGISTERED_OUTPUTS//// Register OR1200 WISHBONE inputs//// (must be undefined/disabled)////`define OR1200_REGISTERED_INPUTS//// Disable bursts if they are not supported by the// memory subsystem (only affect cache line fill)////`define OR1200_NO_BURSTS////// WISHBONE retry counter range//// 2^value range for retry counter. Retry counter// is activated whenever *wb_rty_i is asserted and// until retry counter expires, corresponding// WISHBONE interface is deactivated.//// To disable retry counters and *wb_rty_i all together,// undefine this macro.////`define OR1200_WB_RETRY 7//// WISHBONE Consecutive Address Burst//// This was used prior to WISHBONE B3 specification// to identify bursts. It is no longer needed but// remains enabled for compatibility with old designs.//// To remove *wb_cab_o ports undefine this macro.//`define OR1200_WB_CAB//// WISHBONE B3 compatible interface//// This follows the WISHBONE B3 specification.// It is not enabled by default because most// designs still don't use WB b3.//// To enable *wb_cti_o/*wb_bte_o ports,// define this macro.////`define OR1200_WB_B3//// Enable additional synthesis directives if using// _Synopsys_ synthesis tool////`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES//// Enables default statement in some case blocks// and disables Synopsys synthesis directive full_case//// By default it is enabled. When disabled it// can increase clock frequency.//`define OR1200_CASE_DEFAULT//// Operand width / register file address width//// (DO NOT CHANGE)//`define OR1200_OPERAND_WIDTH 32`define OR1200_REGFILE_ADDR_WIDTH 5//// l.add/l.addi/l.and and optional l.addc/l.addic// also set (compare) flag when result of their// operation equals zero//// At the time of writing this, default or32// C/C++ compiler doesn't generate code that// would benefit from this optimization.//// By default this optimization is disabled to// save area.////`define OR1200_ADDITIONAL_FLAG_MODIFIERS//// Implement l.addc/l.addic instructions and SR[CY]//// At the time of writing this, or32// C/C++ compiler doesn't generate l.addc/l.addic// instructions. However or32 assembler// can assemble code that uses l.addc/l.addic insns.//// By default implementation of l.addc/l.addic// instructions and SR[CY] is disabled to save// area.//// [Because this define controles implementation// of SR[CY] write enable, if it is not enabled,// l.add/l.addi also don't set SR[CY].]////`define OR1200_IMPL_ADDC//// Implement optional l.div/l.divu instructions//// By default divide instructions are not implemented// to save area and increase clock frequency. or32 C/C++// compiler can use soft library for division.//// To implement divide, multiplier needs to be implemented.////`define OR1200_IMPL_DIV//// Implement rotate in the ALU//// At the time of writing this, or32// C/C++ compiler doesn't generate rotate// instructions. However or32 assembler// can assemble code that uses rotate insn.// This means that rotate instructions// must be used manually inserted.//// By default implementation of rotate// is disabled to save area and increase// clock frequency.////`define OR1200_IMPL_ALU_ROTATE//// Type of ALU compare to implement//// Try either one to find what yields// higher clock frequencyin your case.////`define OR1200_IMPL_ALU_COMP1`define OR1200_IMPL_ALU_COMP2//// Implement multiplier//// By default multiplier is implemented//`define OR1200_MULT_IMPLEMENTED//// Implement multiply-and-accumulate//// By default MAC is implemented. To// implement MAC, multiplier needs to be// implemented.//`define OR1200_MAC_IMPLEMENTED//// Low power, slower multiplier//// Select between low-power (larger) multiplier// and faster multiplier. The actual difference// is only AND logic that prevents distribution// of operands into the multiplier when instruction// in execution is not multiply instruction////`define OR1200_LOWPWR_MULT//// Clock ratio RISC clock versus WB clock//⌨️ 快捷键说明
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