or1200_du.v

一个开放的risc

//
// Breakpoint activation register
//
always @(posedge clk or posedge rst)
	if (rst)
		dbg_bp_r <= #1 1'b0;
	else if (!ex_freeze)
		dbg_bp_r <= #1 |except_stop
`ifdef OR1200_DU_DMR1_ST
                        | ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]) & dmr1[`OR1200_DU_DMR1_ST]
`endif
`ifdef OR1200_DU_DMR1_BT
                        | (branch_op != `OR1200_BRANCHOP_NOP) & dmr1[`OR1200_DU_DMR1_BT]
`endif
			;
        else
                dbg_bp_r <= #1 |except_stop;

//
// Write to DMR1
//
`ifdef OR1200_DU_DMR1
always @(posedge clk or posedge rst)
	if (rst)
		dmr1 <= 2'b00;
	else if (dmr1_sel && spr_write)
		dmr1 <= #1 spr_dat_i[23:22];
`else
assign dmr1 = 2'b00;
`endif

//
// DMR2 bits tied to zero
//
`ifdef OR1200_DU_DMR2
assign dmr2 = 32'h0000_0000;
`endif

//
// Write to DSR
//
`ifdef OR1200_DU_DSR
always @(posedge clk or posedge rst)
	if (rst)
		dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};
	else if (dsr_sel && spr_write)
		dsr <= #1 spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0];
`else
assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
`endif

//
// Write to DRR
//
`ifdef OR1200_DU_DRR
always @(posedge clk or posedge rst)
	if (rst)
		drr <= 14'b0;
	else if (drr_sel && spr_write)
		drr <= #1 spr_dat_i[13:0];
	else
		drr <= #1 drr | except_stop;
`else
assign drr = 14'b0;
`endif

//
// Read DU registers
//
`ifdef OR1200_DU_READREGS
always @(spr_addr or dsr or drr or dmr1 or dmr2
`ifdef OR1200_DU_TB_IMPLEMENTED
	or tb_wadr or tbia_dat_o or tbim_dat_o
	or tbar_dat_o or tbts_dat_o
`endif
	)
	casex (spr_addr[`OR1200_DUOFS_BITS]) // synopsys parallel_case
`ifdef OR1200_DU_DMR1
		`OR1200_DU_OFS_DMR1:
			spr_dat_o = {8'b0, dmr1, 22'b0};
`endif
`ifdef OR1200_DU_DMR2
		`OR1200_DU_OFS_DMR2:
			spr_dat_o = dmr2;
`endif
`ifdef OR1200_DU_DSR
		`OR1200_DU_OFS_DSR:
			spr_dat_o = {18'b0, dsr};
`endif
`ifdef OR1200_DU_DRR
		`OR1200_DU_OFS_DRR:
			spr_dat_o = {18'b0, drr};
`endif
`ifdef OR1200_DU_TB_IMPLEMENTED
		`OR1200_DU_OFS_TBADR:
			spr_dat_o = {24'h000000, tb_wadr};
		`OR1200_DU_OFS_TBIA:
			spr_dat_o = tbia_dat_o;
		`OR1200_DU_OFS_TBIM:
			spr_dat_o = tbim_dat_o;
		`OR1200_DU_OFS_TBAR:
			spr_dat_o = tbar_dat_o;
		`OR1200_DU_OFS_TBTS:
			spr_dat_o = tbts_dat_o;
`endif
		default:
			spr_dat_o = 32'h0000_0000;
	endcase
`endif

//
// DSR alias
//
assign du_dsr = dsr;

`ifdef OR1200_DU_TB_IMPLEMENTED
//
// Simple trace buffer
// (right now hardcoded for Xilinx Virtex FPGAs)
//
// Stores last 256 instruction addresses, instruction
// machine words and ALU results
//

//
// Trace buffer write enable
//
assign tb_enw = ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]);

//
// Trace buffer write address pointer
//
always @(posedge clk or posedge rst)
	if (rst)
		tb_wadr <= #1 8'h00;
	else if (tb_enw)
		tb_wadr <= #1 tb_wadr + 8'd1;

//
// Free running counter (time stamp)
//
always @(posedge clk or posedge rst)
	if (rst)
		tb_timstmp <= #1 32'h00000000;
	else if (!dbg_bp_r)
		tb_timstmp <= #1 tb_timstmp + 32'd1;

//
// Trace buffer RAMs
//
RAMB4_S16_S16 tbia_ramb4_s16_0(
	.CLKA(clk),
	.RSTA(rst),
	.ADDRA(tb_wadr),
	.DIA(spr_dat_npc[15:0]),
	.ENA(1'b1),
	.WEA(tb_enw),
	.DOA(),

	.CLKB(clk),
	.RSTB(rst),
	.ADDRB(spr_addr[7:0]),
	.DIB(16'h0000),
	.ENB(1'b1),
	.WEB(1'b0),
	.DOB(tbia_dat_o[15:0])
);

RAMB4_S16_S16 tbia_ramb4_s16_1(
	.CLKA(clk),
	.RSTA(rst),
	.ADDRA(tb_wadr),
	.DIA(spr_dat_npc[31:16]),
	.ENA(1'b1),
	.WEA(tb_enw),
	.DOA(),

	.CLKB(clk),
	.RSTB(rst),
	.ADDRB(spr_addr[7:0]),
	.DIB(16'h0000),
	.ENB(1'b1),
	.WEB(1'b0),
	.DOB(tbia_dat_o[31:16])
);

RAMB4_S16_S16 tbim_ramb4_s16_0(
	.CLKA(clk),
	.RSTA(rst),
	.ADDRA(tb_wadr),
	.DIA(ex_insn[15:0]),
	.ENA(1'b1),
	.WEA(tb_enw),
	.DOA(),

	.CLKB(clk),
	.RSTB(rst),
	.ADDRB(spr_addr[7:0]),
	.DIB(16'h0000),
	.ENB(1'b1),
	.WEB(1'b0),
	.DOB(tbim_dat_o[15:0])
);

RAMB4_S16_S16 tbim_ramb4_s16_1(
	.CLKA(clk),
	.RSTA(rst),
	.ADDRA(tb_wadr),
	.DIA(ex_insn[31:16]),
	.ENA(1'b1),
	.WEA(tb_enw),
	.DOA(),

	.CLKB(clk),
	.RSTB(rst),
	.ADDRB(spr_addr[7:0]),
	.DIB(16'h0000),
	.ENB(1'b1),
	.WEB(1'b0),
	.DOB(tbim_dat_o[31:16])
);

RAMB4_S16_S16 tbar_ramb4_s16_0(
	.CLKA(clk),
	.RSTA(rst),
	.ADDRA(tb_wadr),
	.DIA(rf_dataw[15:0]),
	.ENA(1'b1),
	.WEA(tb_enw),
	.DOA(),

	.CLKB(clk),
	.RSTB(rst),
	.ADDRB(spr_addr[7:0]),
	.DIB(16'h0000),
	.ENB(1'b1),
	.WEB(1'b0),
	.DOB(tbar_dat_o[15:0])
);

RAMB4_S16_S16 tbar_ramb4_s16_1(
	.CLKA(clk),
	.RSTA(rst),
	.ADDRA(tb_wadr),
	.DIA(rf_dataw[31:16]),
	.ENA(1'b1),
	.WEA(tb_enw),
	.DOA(),

	.CLKB(clk),
	.RSTB(rst),
	.ADDRB(spr_addr[7:0]),
	.DIB(16'h0000),
	.ENB(1'b1),
	.WEB(1'b0),
	.DOB(tbar_dat_o[31:16])
);

RAMB4_S16_S16 tbts_ramb4_s16_0(
	.CLKA(clk),
	.RSTA(rst),
	.ADDRA(tb_wadr),
	.DIA(tb_timstmp[15:0]),
	.ENA(1'b1),
	.WEA(tb_enw),
	.DOA(),

	.CLKB(clk),
	.RSTB(rst),
	.ADDRB(spr_addr[7:0]),
	.DIB(16'h0000),
	.ENB(1'b1),
	.WEB(1'b0),
	.DOB(tbts_dat_o[15:0])
);

RAMB4_S16_S16 tbts_ramb4_s16_1(
	.CLKA(clk),
	.RSTA(rst),
	.ADDRA(tb_wadr),
	.DIA(tb_timstmp[31:16]),
	.ENA(1'b1),
	.WEA(tb_enw),
	.DOA(),

	.CLKB(clk),
	.RSTB(rst),
	.ADDRB(spr_addr[7:0]),
	.DIB(16'h0000),
	.ENB(1'b1),
	.WEB(1'b0),
	.DOB(tbts_dat_o[31:16])
);

`else
assign tbia_dat_o = 32'h0000_0000;
assign tbim_dat_o = 32'h0000_0000;
assign tbar_dat_o = 32'h0000_0000;
assign tbts_dat_o = 32'h0000_0000;

`endif	// OR1200_DU_TB_IMPLEMENTED

`else	// OR1200_DU_IMPLEMENTED

//
// When DU is not implemented, drive all outputs as would when DU is disabled
//
assign dbg_bp_o = 1'b0;
assign du_dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};

//
// Read DU registers
//
`ifdef OR1200_DU_READREGS
assign spr_dat_o = 32'h0000_0000;
`ifdef OR1200_DU_UNUSED_ZERO
`endif
`endif

`endif

endmodule