top.v

hrisc cpu

//-----------------------------------------------------------------------------
//
// Author: John Clayton
// Date  : Aug.   20, 2002
// Update: Nov.   20, 2002 Obtained this file from "build_13" project.
// Update: Dec.    4, 2002 In testing with XST, realized that clock skew was
//                         causing major problems.  Added clock BUFG instances
//                         which took care of the skew problems.  Also, added
//                         clock doubling, with DDS to synthesize frequencies
//                         up to the input frequency, with BUFG.
//
// Description
//-----------------------------------------------------------------------------
// This targets an XC2S200 board which was created for educational purposes.
//
// There are:
//    8  LEDs (led[7:0])
//    4  switches (switch[3:0])
//    1  clock of 32.000 MHz clock, present on GCLK1
//    1  clock of 49.152 MHz clock, present on GCLK0
//    4  lines of ps2 clock input (port A in documentation notes)
//    4  lines of ps2 data input (port A in documentation notes)
//    16 lines of LCD panel control (port B in documentation notes)
//    2  lines of rs232 serial connection (port C in documentation notes)
//-----------------------------------------------------------------------------
//
// NOTE: This build is for testing out an automatic BAUD rate generator
//
// The following 'include line must be used with Synplify to create EDIF
// The line must be commented for ModelSim.
//`include "d:\synplicity\synplify_70\lib\xilinx\virtex.v"

module top (
  sys_clk_0,
  switch,
  led,
  lcd_drive,
  rs232_rxd,
  rs232_txd,
  port_e,
  port_f,
  dat_o
  );

// I/O declarations
input sys_clk_0;      // 49.152 MHz
input [3:0] switch;
input rs232_rxd;
input [7:0] port_f;

output [7:0] led;
output [15:0] lcd_drive;
output rs232_txd;
output [13:0] port_e;
output [15:0] dat_o;

// Internal signal declarations

wire [4:0] r0_wire;  // "Read" regs.  Used to "hold" pin locations, so that
                     // the synthesis tools do not complain about these pins
                     // being present in the constraints file and not in the
                     // design...

wire [7:0] input_f = ~port_f;  // Port f input inverted (bcd thumbwheel)

     // System Clock signals
wire sys_clk_0g;
wire sys_clk_variable_unbuffered;
wire sys_clk_variable;
wire sys_clk_variable_dll;
wire sys_clk_half_variable_dll;
wire sys_clk_variable_half;
wire sys_clk_lcd;
wire sys_clk_lcd_ram;
wire sys_clk2x;
wire locked2x_delay;
wire reset4x;
wire [8:0] sys_clk_freq;

     // Signals from risc processor
wire [15:0] risc_aux_adr;     // AUX (expansion) bus
wire        risc_aux_we;      // AUX we
wire [15:0] risc_prog_dat;    // Program data
wire [12:0] risc_prog_adr;    // (Up to 8k words possible)
wire [8:0]  risc_ram_adr;     // RAM file address
wire [7:0]  risc_ram_dat_o;   // RAM file data
wire [7:0]  risc_ram_dat_i;   // RAM file data
wire        risc_ram_we;      // RAM we
wire        risc_stb;         // Clock enable for risc processor

     // Signals from rs232_syscon
wire [15:0] adr;        // A side address
wire [7:0] dat;         // A side data
wire we;
wire stb;
wire rst;
wire master_br;

    // Address decode signals
wire       code_space;  // High for access to code space (AUX bus)
wire       rgb_space;   // High for access to rgb space (AUX bus)
wire       io_space;    // High for access to I/O space (AUX bus)
wire [1:0] io_sel;      // 1 of these is active high for I/O space accesses

    // Hardware breakpoint and single stepping signals
wire [12:0] break_prog_adr;  // For hardware breakpoint on prog. adr
wire [13:0] break_prog_dat;  // For hardware breakpoint on prog. dat
wire [ 1:0] break_enable;    // bit 1: enables dat BP, bit 0: enables adr BP
wire        breakpoint;      // 1 = any breakpoint condition encountered.
reg  [ 5:0] step_count;      // Number of steps remaining to execute
wire [ 5:0] clocks_to_step;  // Desired number of steps to execute
wire        begin_stepping;       // Automatically resets itself when written!
wire        stepping_active;      // 1 during single stepping
wire        reset_single_stepper; // 1 during breakpoint or reset
wire [ 3:0] processor_control; // For manipulating the processor
wire        run_free;          // Allows processor to run constantly
wire        forced_reset;      // Forces the processor into reset
wire        bus_rdy;           // 1 = processor can execute this clock cycle.

    // Processor interrupt signals
wire slow_int;                 // For checking long interrupt requests
wire periodic_int;             // For checking short interrupt requests
wire periodic_int_enable;      // Enables periodic interrupt
reg  [21:0] int_counter;

    // A side RAM signals
wire [7:0] code_ram_dat_o;
wire [2:0] rgb_ram_dat_o;
wire [7:0] regfile_ram_dat_o;

    // B side (Peripheral side) RAM signals
wire [2:0]  pixel_dat;
wire [13:0] pixel_adr;   // (12288 pixels addressed)

    // Other...
wire reset = switch[0];  // Simply a renaming exercise

wire [13:0] risc_debug;

//--------------------------------------------------------------------------
// Clock generation
//--------------------------------------------------------------------------

// This Xilinx DLL provides clock doubling.
// It also provides delay compensation, duty cycle correction and it can
// divide by 1.5, 2, 2.5, 3, 4, 5, 8 or 16.  The divided clock output
// also will have 50% duty cycle, regardless of the division factor.
// The CLKDV_DIVIDE property determines the division factor (default = 2).

CLKDLL dll2x (
              .CLKIN(sys_clk_0),
              .CLKFB(sys_clk2x),
              .RST(reset),
              .CLK0(sys_clk),
              .CLK90(),
              .CLK180(),
              .CLK270(),
              .CLK2X(clk2x_dll),
              .CLKDV(sys_clk_lcd),
              .LOCKED(locked2x)
              );

BUFG  clk2xg (
              .I(clk2x_dll),
              .O(sys_clk2x)
              );

assign sys_clk_lcd_ram = sys_clk;

// This block generates a variable frequency system clock
assign sys_clk_freq = input_f + 1;
square_wave_dds #(
                  9       // DDS counter length
                  )
dds1
   (
    .clk(sys_clk2x),
    .clk_en(1'b1),
    .reset(reset),
    .frequency(sys_clk_freq),
    .clk_out(sys_clk_variable_unbuffered)
    );


SRL16 rstsrl (
              .D(locked2x),
              .CLK(sys_clk2x),
              .Q(locked2x_delay),
              .A3(1'b1),
              .A2(1'b1),
              .A1(1'b1),
              .A0(1'b1)
              );

assign reset4x = !locked2x_delay;

CLKDLL dllvar (
              .CLKIN(sys_clk_variable_unbuffered),
              .CLKFB(sys_clk_variable),
              .RST(reset4x),
              .CLK0(sys_clk_variable_dll),
              .CLK90(),
              .CLK180(),
              .CLK270(),
              .CLK2X(sys_clk2x_variable_dll),
              .CLKDV(sys_clk_half_variable_dll),
              .LOCKED(locked2x_var)
              );


// Choose one of the following sets of BUFG instantiations, for clock speeds
// in the low range (first set) or twice that speed (second set.)
// The "low range" provides sys_clk_variable which is synthesized by the DDS
// from a 2x clock, so that its output ranges up to almost the frequency of
// the sys_clk_0 input.

BUFG  clkbuf1 (
               .I(sys_clk_variable_dll),
               .O(sys_clk_variable)
               );

BUFG  clkbuf2 (
               .I(sys_clk_half_variable_dll),
               .O(sys_clk_variable_half)
               );

//BUFG  clkbuf1 (
//               .I(sys_clk2x_variable_dll),
//               .O(sys_clk_variable)
//               );
//
//BUFG  clkbuf2 (
//               .I(sys_clk_variable_dll),
//               .O(sys_clk_variable_half)
//               );

//--------------------------------------------------------------------------
// Instantiations
//--------------------------------------------------------------------------

// This is for monitoring signals using a logic analyzer
assign dat_o = 0;
assign port_e = 0;


// This block runs the flat panel display (5x5 pixels)
vga_128_by_92 lcd_block (
  .lcd_clk(sys_clk_lcd),
  .lcd_reset(reset),
  .pixel_dat_i(pixel_dat),
  .pixel_adr_o(pixel_adr),
  .lcd_drive(lcd_drive)
  );

// This block is the risc microcontroller
assign risc_stb = (bus_rdy || rst);
risc16f84_clk2x 
  processor1