risc16f84_clk2x.v

hrisc cpu

//---------------------------------------------------------------------------
// RISC 16F84 "clk2x" core
//
// This file is part of the "risc_16F84" project.
// http://www.opencores.org/cores/risc_16F84
// 
//
// Description: See description below (which suffices for IP core
//                                     specification document.)
//
// Copyright (C) 1999 Sumio Morioka (original VHDL design version)
// Copyright (C) 2001 John Clayton and OPENCORES.ORG (this Verilog version)
//
// NOTE: This source code is free for educational/hobby use only.  It cannot
// be used for commercial purposes without the consent of Microchip
// Technology incorporated.
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation;  either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source.
// If not, download it from http://www.opencores.org/lgpl.shtml
//
//---------------------------------------------------------------------------
//
// Author: John Clayton
// Date  : January 29, 2002
//
// (NOTE: Date formatted as day/month/year.)
// Update: 29/01/02 copied this file from memory_sizer.v (pared down).
//                  Translated the module and signal declarations.
//                  Transformed the instruction wires to lowercase.
//                  Transformed the addressing wires to lowercase.
// Update: 31/01/02 Translated the instruction decoder.
// Update:  5/02/02 Determined that stack is simply a circular buffer of
//                  8 locations, 13 bits per location.  Started translating
//                  "main_efsm" process.  Added all code from piccore.vhd
//                  into this file for eventual translation.  Concluded that
//                  "stack_full_node" is not needed.
// Update:  6/02/02 Translated the "ram_i_node" if/else precedural assignment.
// Update:  7/02/02 Changed all := to <=, changed all '0' to 0 and '1' to 1.
//                  Replaced all " downto " with ":".
//                  Finished translating QRESET state.
// Update: 20/02/02 Replaced all instances of Qreset with QRESET_PP.  Also
//                  replaced other state designations with their new names.
//                  Finished translating Q1, Q2 states.
// Update: 22/02/02 Translated section 2-4-1-1 (aluout register)
// Update: 27/02/02 Replaced all "or" with "||" in if statements
//                  Replaced all "and" with "&&" in if statements.
//                  Replaced all "not" with "~" in if statements.
//                  Finished translating Q3,Q4 states.
//                  Translated output signal assignments at end of code.
//                  Translated interrupt trigger processes.
// Update: 28/02/02 Finished translation of WDT and TMR0 prescaler.
//                  Trimmed line length to 80 characters throughout.
//                  Prepared to attempt initial syntax checking.
//                  Cleaned up some naming conventions, and verified that
//                  all I/O pins have _i or _o appended in the body of the
//                  code.
// Update: 03/04/02 Changed "progdata_i" to "prog_dat_i" Also changed
//                  "progadr_o" to "prog_adr_o"
// Update: 04/04/02 Created new file "risc16f84_lite.v"  This file is reduced
//                  and simplified from the original "risc16f84.v" file.
//                  Specifically, I am removing EEPROM support, and 
//                  consolidating porta and portb I/O pins so that they
//                  are bidirectional.
// Update: 04/04/02 Created a new file "risc16f84_small.v"  This file is
//                  further reduced and simplified from "risc16f84_lite.v"
//                  Specifically, I am removing the prescaler, TMR0 and WDT.
//                  Also, I am removing support for portb interrupts, leaving
//                  only rb0/int as an interrupt source.  This pin will be
//                  the only way to wake up from the SLEEP instruction...
//                  Obviously, the CLEARWDT instruction will no longer do
//                  anything.
// Update: 05/04/02 Removed the "powerdown_o", "startclk_o" and "clk_o" pins
//                  from the small design.  Also removed "rbpu_o", so if you
//                  want pullups, you have to add them explicitly in the
//                  constraints file, and option_reg[7] doesn't control them.
// Update: 08/04/02 Decided to modify "risc16f84_small.v" in order to try for
//                  more performance (only 2 states per instruction!)
//                  The new file is called "risc16f84_clk2x.v"  The resulting
//                  code was synthesized, but not tested yet.
// Update: 11/04/02 Decided to remove porta and portb from this unit, and add
//                  instead an auxiliary bus, which is intended to allow I/O
//                  using an indirect approach, similar to using the FSR.
//                  However, the aux_adr_o is 16 bits wide, so that larger
//                  RAM may be accessed indirectly by the processor... The use
//                  of FSR for this purpose proved undesirable, since any new
//                  page of RAM contains "holes" to accomodate the registers
//                  in the first 12 locations (including FSR!) so that large
//                  contiguous blocks of memory could not be accessed in an
//                  effective way.  This auxiliary bus solves that problem.
//                  Since this processor is implemented inside of an FPGA,
//                  and it is not a goal to maintain compatibility with
//                  existing libraries of code, there is no need to maintain
//                  porta and portb in the hardware.
//                  The aux_adr_lo and aux_adr_hi registers are located at
//                  88h and 89h, and the aux_dat_io location is decoded at
//                  08h.
//                  Also, changed to using "ram_we_o" instead of "readram_o"
//                  and "writeram_o"
// Update: 16/04/02 Added clock enable signal, for processor single stepping.
//                  "aux_dat_io" is only driven when "clk_en_i" is high...
// Update: 17/04/02 Removed "reset_condition" and moved "inc_pc_node" out of
//                  the clocking area, making it non-registered.  In fact, I
//                  moved everything other than the state machine out of the
//                  clocked logic section.  Changed "aluout_reg" to "aluout"
//                  since it is no longer registered.
// Update: 26/04/02 Fixed bug in aluout logic.  The AND and OR functions were
//                  coded with logical AND/OR instead of bitwise AND/OR!
// Update: 26/04/02 Changed location of aux_adr_lo and aux_adr_hi registers
//                  to 05h and 06h, respectively.  This was done to save
//                  code space because when using the aux data bus, no bank
//                  switching is necessary since they will now reside in the
//                  same bank.
// Update: 01/05/02 Fixed another bug -- the rrf and rlf instructions were
//                  coded incorrectly.
// Update: 03/05/02 Fixed another bug -- the carry bit was incorrect (the
//                  problem was discovered while performing SUBWF X,W where
//                  W contained 0 and X contained 1. (1-0).  The logic for
//                  the carry bit appears to have been incorrect even in
//                  the original VHDL code by Sumio Morioka.
// Update: 11/18/02 Fixed bug in PCL addressing mode (near line 791)
//                  Removed parameters associated with WDT.
// Update: 11/25/02 Re-wrote much of the main FSM.  Attempted to generate logic
//                  to recognize the falling edge of an interrupt, and was
//                  unsuccessful (not simulation, actual hardware tests.)
//                  Realized that falling edge interrupt can be equivalent to
//                  rising edge interrupt with a NOT gate on the signal.  Since
//                  NOTs are practically free inside of an FPGA, decided to
//                  abandon the negative edge aspect of recognizing interrupts.
//                  Therefore, removed the "option_reg" since it is no longer
//                  needed in this design.
//
// Description
//---------------------------------------------------------------------------
// This logic module implements a small RISC microcontroller, with functions
// and instruction set very similar to those of the Microchip 16F84 chip.
// This work is a translation (from VHDL to Verilog) of the "CQPIC" design
// published in 1999 by Sumio Morioka of Japan, and published in the December
// 1999 issue of "Transistor Gijutsu Magazine."  The translation was performed
// by John Clayton, without the use of any translation tools.
//
// Original version used as basis for translation:  CQPIC version 1.00b
//                                                  (December 10, 2000)
//
// Further revisions and re-writing have been completed on this code by John
// Clayton.  The interrupt mechanism has been completely re-done, and the
// way in which the program counter is generated is expressed in a new way.
//
// In the comments, a "cycle" is defined as a processor cycle of 2 states.
// Thus, passing through states Q2_PP and Q4_PP completes one cycle.
// The numbers "1-3" and so forth are left from the comments in the original
// source code used as the basis of the translation.
//---------------------------------------------------------------------------

`define STATEBIT_SIZE 2      // Size of state machine register (bits)


module risc16f84_clk2x (
  prog_dat_i,           // [13:0] ROM read data
  prog_adr_o,           // [12:0] ROM address
  ram_dat_i,            // [7:0] RAM read data
  ram_dat_o,            // [7:0] RAM write data
  ram_adr_o,            // [8:0] RAM address; ram_adr[8:7] indicates RAM-BANK
  ram_we_o,             // RAM write strobe (H active)
  aux_adr_o,            // [15:0] Auxiliary address bus
  aux_dat_io,           // [7:0] Auxiliary data bus (tri-state bidirectional)
  aux_we_o,             // Auxiliary write strobe (H active)
  int0_i,               // PORT-B(0) INT
  reset_i,              // Power-on reset (H active)
  clk_en_i,             // Clock enable for all clocked logic
  clk_i                 // Clock input
);


// You can change the following parameters as you would like
parameter STACK_SIZE_PP      = 8;   // Size of PC stack
parameter LOG2_STACK_SIZE_PP = 3;   // Log_2(stack_size)

// State definitions for state machine, provided as parameters to allow
// for redefinition of state values by the instantiator if desired.
parameter Q2_PP     = 2'b00;  // state Q2
parameter Q4_PP     = 2'b01;  // state Q4
parameter QINT_PP   = 2'b10;  // interrupt state (substitute for Q4)
parameter QSLEEP_PP = 2'b11;  // sleep state


// I/O declarations

       // program ROM data bus/address bus
input  [13:0] prog_dat_i;   // ROM read data
output [12:0] prog_adr_o;   // ROM address

       // data RAM data bus/address bus/control signals
input  [7:0] ram_dat_i;     // RAM read data
output [7:0] ram_dat_o;     // RAM write data
output [8:0] ram_adr_o;     // RAM address; ram_adr[8:7] indicates RAM-BANK
output ram_we_o;            // RAM write strobe (H active)

       // auxiliary data bus/address bus/control signals
output [15:0] aux_adr_o;    // AUX address bus
inout  [7:0]  aux_dat_io;   // AUX data bus
output aux_we_o;            // AUX write strobe (H active)

       // interrupt input
input  int0_i;              // INT

       // CPU reset
input  reset_i;             // Power-on reset (H active)

       // CPU clock
input  clk_en_i;            // Clock enable input
input  clk_i;               // Clock input


// Internal signal declarations

     // User registers
reg  [7:0] w_reg;            // W
reg  [12:0] pc_reg;          // PCH/PCL -- Address currently being fetched
reg  [12:0] old_pc_reg;      // Address fetched previous to this one.
reg  [7:0] status_reg;       // STATUS
reg  [7:0] fsr_reg;          // FSR
reg  [4:0] pclath_reg;       // PCLATH
reg  [7:0] intcon_reg;       // INTCON
reg  [7:0] aux_adr_hi_reg;   // AUX address high byte
reg  [7:0] aux_adr_lo_reg;   // AUX address low byte

     // Internal registers for controlling instruction execution
reg  [13:0] inst_reg;        // Holds fetched op-code/operand
reg  [7:0]  aluinp1_reg;     // data source (1 of 2)
reg  [7:0]  aluinp2_reg;     // data source (2 of 2)
reg  c_in;                   // Used with ALU data sources.
reg  exec_stall_reg;         // if H (i.e. after GOTO etc), stall execution.

     // Stack
                             // stack (array of data-registers)
reg  [12:0] stack_reg [STACK_SIZE_PP-1:0];
                             // stack pointer
reg  [LOG2_STACK_SIZE_PP-1:0] stack_pnt_reg;
wire [12:0] stack_top;       // More compatible with sensitivity list than
                             // "stack_reg[stack_pnt_reg]"

     // Interrupt registers/nodes
wire int_condition;          // Indicates that an interrupt should be recognized
wire intrise;                // High indicates edge was detected
reg  intrise_reg;            // detect positive edge of PORT-B inputs
     // Synchronizer for interrupt
reg  inte_sync_reg;

     // State register
reg  [`STATEBIT_SIZE-1:0] state_reg;
reg  [`STATEBIT_SIZE-1:0] next_state_node;

     // Result of decoding instruction -- only 1 is active at a time
wire inst_addlw;
wire inst_addwf;
wire inst_andlw;
wire inst_andwf;
wire inst_bcf;
wire inst_bsf;
wire inst_btfsc;
wire inst_btfss;
wire inst_call;
wire inst_clrf;
wire inst_clrw;
wire inst_comf;
wire inst_decf;
wire inst_decfsz;
wire inst_goto;
wire inst_incf;
wire inst_incfsz;
wire inst_iorlw;
wire inst_iorwf;
wire inst_movlw;
wire inst_movf;
wire inst_movwf;
wire inst_retfie;
wire inst_retlw;
wire inst_ret;
wire inst_rlf;
wire inst_rrf;
wire inst_sleep;
wire inst_sublw;
wire inst_subwf;
wire inst_swapf;
wire inst_xorlw;
wire inst_xorwf;

     // Result of calculating RAM access address
wire [8:0] ram_adr_node;      // RAM access address

     // These wires indicate accesses to special registers... 
     // Only 1 is active at a time.
wire addr_pcl;