78_alu_inputs.vhd

这是一个对于初学者很好的vhdl实验的一些例子,希望站长的支持哦

--------------------------------------------------------------------------------
--
--   AM2901 Benchmark
--
-- Source: AMD data book
--
--------------------------------------------------------------------------------

------------------------------------------------------HS
--	types and mvl_functions are moved in l2901_lib
--  so that they are not needed to complie every time
--  modified by hanshu,June 4,1998
------------------------------------------------------HS
LIBRARY L2901_LIB;
USE L2901_LIB.types.all;
USE L2901_LIB.MVL7_functions.all;

USE L2901_LIB.SYNTHESIS_TYPES.all;

entity alu_inputs is
      port (
            Aadd, Badd : in  integer; 
	        Q, D       : in  MVL7_vector(3 downto 0);
            I          : in  MVL7_vector(8 downto 0); 
            RE, S      : out MVL7_vector(3 downto 0)
           );
end alu_inputs;

architecture alu_inputs of alu_inputs is

  type Memory is array (integer range <>) of MVL7_vector(3 downto 0);
  signal RAM : 
	Memory(15 downto 0) := ( 
					("0000"),
					("0000"),
					("0000"),
					("0000"),
					("0000"),
					("0000"),
					("0000"),
					("0000"),
					("0000"),
					("0000"),
					("0000"),
					("0000"),
					("0000"),
					("0000"),
					("0100"),
					("1000"));
  signal A, B : MVL7_vector(3 downto 0);

begin

A <= RAM(Aadd);
B <= RAM(Badd);

-- SELECT THE SOURCE OPERANDS FOR ALU. SELECTED OPERANDS ARE "RE" AND "S".

with I(2 downto 0) select
  RE <= A when "000" | "001",
       "0000" when "010" | "011" | "100",
       D when others;

with I(2 downto 0) select
  S <= A when "100" | "101",
       B when "001" | "011",
       "0000" when "111",
       Q when others;

end alu_inputs;