26_test_74s.vhd

这是一个对于初学者很好的vhdl实验的一些例子,希望站长的支持哦

--Page          :307,308

--Objective     :'TRANSACTION and reso;ved signals

--Filename      :test_74.vhd

--Author        :Joseph Pick
--Update        :cdy 1998 4

entity Test_74s is
end Test_74s;

architecture Behave_1 of Test_74s is

  type Logic4 is ('x','0','1','z');
  type Logic4_Vector is array (NATURAL range <> ) of Logic4;
  type Logic4_Table is array (Logic4,Logic4) of Logic4;

  constant Table  : logic4_Table := (('x','x','x','x'),
									 ('x','0','x','0'),
									 ('x','x','1','1'),
									 ('x','0','1','z'));
  function Tristate_RF (V :Logic4_Vector) return Logic4 is
	  variable Result : Logic4 := 'z'; 
  begin
	for I in V'RANGE loop
	   Result := Table (Result ,V(I));
	   exit when Result = 'x';
    end loop;
	return Result;
  
  end Tristate_RF;

	 subtype Tristate_RS is Tristate_RF Logic4;
	 signal Signal_Tristate_RS_S : Tristate_RS := 'z';
	 signal Signal_RS_1 : Logic4 ;
	 signal Signal_RS_2 : Logic4 ;
	 signal Count : NATURAL := 0;
	 signal Sevent : NATURAL := 0;

begin 

res_1:
process
begin
   Signal_Tristate_RS_S <= '1';
   Signal_RS_1 <= '1';
   wait for 10 ns;
   Signal_Tristate_RS_S <= '1';
   Signal_RS_1 <= '1';
   wait for 10 ns;
   Signal_Tristate_RS_S <= '1';
   Signal_RS_1 <= '1';
   wait for 10 ns;
   Signal_Tristate_RS_S <= '1';
   Signal_RS_1 <= '1';
   wait for 10 ns;
   Signal_Tristate_RS_S <= '0';
   Signal_RS_1 <= '0';
   wait for 10 ns;
   Signal_Tristate_RS_S <= '0';
   Signal_RS_1 <= '0';
   wait for 10 ns;
   Signal_Tristate_RS_S <= '0';
   Signal_RS_1 <= '0';
   wait for 10 ns;
   Signal_Tristate_RS_S <= 'x';
   Signal_RS_1 <= 'x';
   wait for 10 ns;
   Signal_Tristate_RS_S <= 'x';
   Signal_RS_1 <= 'x';
   wait for 10 ns;
   Signal_Tristate_RS_S <= 'z';
   Signal_RS_1 <= 'z';
   wait for 10 ns;
   wait;
end process res_1;

res_2:
process
begin
   Signal_Tristate_RS_S <= '0';
   Signal_RS_2 <= '0';
   wait for 10 ns;
   Signal_Tristate_RS_S <= '1';
   Signal_RS_2 <= '1';
   wait for 10 ns;
   Signal_Tristate_RS_S <= 'z';
   Signal_RS_2 <= 'z';
   wait for 10 ns;
   Signal_Tristate_RS_S <= 'x';
   Signal_RS_2 <= 'x';
   wait for 10 ns;
   Signal_Tristate_RS_S <= '0';
   Signal_RS_2 <= '0';
   wait for 10 ns;
   Signal_Tristate_RS_S <= 'z';
   Signal_RS_2 <= 'z';
   wait for 10 ns;
   Signal_Tristate_RS_S <= 'x';
   Signal_RS_2 <= 'x';
   wait for 10 ns;
   Signal_Tristate_RS_S <= 'x';
   Signal_RS_2 <= 'x';
   wait for 10 ns;
   Signal_Tristate_RS_S <= 'z';
   Signal_RS_2 <= 'z';
   wait for 10 ns;
   Signal_Tristate_RS_S <= 'z';
   Signal_RS_2 <= 'z';
   wait for 10 ns;
   wait;
end process res_2;

 Test_Proc:
 process
 begin
   wait on Signal_Tristate_RS_S'TRANSACTION;
   --*****         REASULT          **********
   --As expected, wait condition passed when z was placed 
   --on one of the signal's mullti-source.

   if Signal_Tristate_RS_S'TRANSACTION'EVENT=FALSE
   then		Sevent <= Sevent +1;
   end if;
   Count <= Count + 1;
 end process Test_Proc;
end Behave_1;