58_decoder.vhd

这是一个对于初学者很好的vhdl实验的一些例子,希望站长的支持哦

-- The eneity declaration of INVERTER
------------------------
entity B_INV is
------------------------
   port(
        I1 : in bit;
        O1 : out bit
       );
end B_INV;

-- The architecture body of the INVERTER entity declaration
------------------------------
architecture FUNC of B_INV is
------------------------------
begin 
   O1 <= not I1;
end FUNC;



--------------------
entity B_AND2 is
--------------------
   port(
        I1 : in bit;
        I2 : in bit;
        O1 : out bit
       );
end B_AND2;

------------------------------
architecture FUNC of B_AND2 is
------------------------------
begin
  O1 <= (I1 and I2 );
end FUNC;
 

----------------------------------------------
entity Decoder is
----------------------------------------------
   port (
		 Sel:Bit_vector( 1 downto 0 );
		 Dout:out Bit_vector( 3 downto 0 )
	     );


end Decoder;

---------------------------------------------
 architecture Structure of Decoder is
---------------------------------------------

 component And2
	port(I1,I2:Bit;O1:out Bit);
 end component;

 component Inverter
	port(I1:BIt;O1:out Bit);
 end component;

 signal Sel_bar : Bit_vector(1 downto 0);

 for Inv_0,Inv_1 : Inverter use entity work.B_INV(FUNC);

 for And_0,And_1,And_2,And_3 : And2 use entity work.B_AND2(FUNC);

 begin
		Inv_0:Inverter
		  port map(Sel(0),Sel_bar(0) );

		Inv_1:Inverter
		  port map(Sel(1),Sel_bar(1) );

        And_0:And2
		  port map(Sel_bar(1),Sel_bar(0),Dout(0) );

        And_1:And2
		  port map(Sel_bar(1),Sel(0),Dout(1) );

        And_2:And2
		  port map(Sel(1),Sel_bar(0),Dout(2) );

        And_3:And2
		  port map(Sel(1),Sel(0),Dout(3) );

  end structure;

----------------------------------------------------
  entity test_decoder is
----------------------------------------------------

  end test_decoder; 

----------------------------------------------------
  architecture BENCH of test_decoder is
---------------------------------------------------

  component decoder 

   port (
		 Sel:Bit_vector( 1 downto 0 );
		 Dout:out Bit_vector( 3 downto 0 )
	     );

  end component;

  for I1:  decoder  use entity work.decoder(structure);

  signal t_S : Bit_vector( 1 downto 0 ); 
  signal t_O : Bit_vector( 3 downto 0 );

  begin
     I1 : decoder 
          port map (
                     Sel => t_S,
                     Dout =>t_O
                     );

     driver: process
     begin
         t_S <= "00";
		 wait for 100 ns; 
		 assert(t_O = "0001")
		 report 
		 "Assert0  t_O /= 0001"
		 severity warning;

         t_S <= "01";
		 wait for 100 ns; 
		 assert(t_O = "0010")
		 report 
		 "Assert1  t_O /= 0010"
		 severity warning;


         t_S <= "10";
		 wait for 100 ns; 
		 assert(t_O = "0100")
		 report 
		 "Assert2  t_O /= 0100"
		 severity warning;

         t_S <= "11";
		 wait for 100 ns; 
		 assert(t_O = "1000")
		 report 
		 "Assert2  t_O /= 1000"
		 severity warning;

			wait for 200 ns;
          assert false
          report "----End of Simulation----"
          severity error;
      end process;
 
  end BENCH;