66_testfir.vhd

这是一个对于初学者很好的vhdl实验的一些例子,希望站长的支持哦

Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.SIGNED_ARITH.all;


entity tb_e is
end tb_e;

architecture tb_a of tb_e is
signal clock,reset:std_logic;
signal instream: signed ( 7 downto 0);
signal outstream: signed ( 16 downto 0);
component fir -- declare the filter
port (clk,reset: in std_logic;
      sample: in signed (7 downto 0);
      result: out signed (16 downto 0));
end component;

      for filter:fir use entity work.fir(beh);
begin
   filter:fir  --instantiate the filter
   port map(clk=>clock,
            reset=>reset,
            sample=>instream,
            result=>outstream);
   clockgen:process
   begin
        clock<='1';
        loop
            wait for 50 ns;
            clock<=not clock;
        end loop;
  end process clockgen;

  po_reset: process 
  begin
       reset<='1';
       wait for 102 ns;
       reset<='0';
       wait;
  end process po_reset;

  stimulus: process 
  begin
   instream<="00000000";
   wait for 302 ns;
   instream<="00000010";
   wait for 302 ns;
   instream<="00001000";
   wait for 302 ns;
   instream<="10100000";
   wait for 302 ns;
   assert false report "End of Simulation" SEVERITY error;
   end process stimulus;
end tb_a;