hdpdeps.ref

vhdl实例教程

V1 10
FL D:/BJ_xilinx/demo_led/Memec_3SLC_VHDL_ISE63/seven_seg.vhd 2005/08/29.11:42:32
EN work/SEVEN_SEG       FL D:/BJ_xilinx/demo_led/Memec_3SLC_VHDL_ISE63/seven_seg.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_UNSIGNED
AR work/SEVEN_SEG/SEVEN_SEG_ARCH \
      FL D:/BJ_xilinx/demo_led/Memec_3SLC_VHDL_ISE63/seven_seg.vhd \
      EN work/SEVEN_SEG CP CLKDLL_DIVIDE
FL D:/BJ_xilinx/demo_led/Memec_3SLC_VHDL_ISE63/clkdll_divide.vhd 2004/12/20.06:39:44
EN work/CLKDLL_DIVIDE \
      FL D:/BJ_xilinx/demo_led/Memec_3SLC_VHDL_ISE63/clkdll_divide.vhd \
      PB ieee/STD_LOGIC_1164 PH unisim/VCOMPONENTS
AR work/CLKDLL_DIVIDE/BEHAVIORAL \
      FL D:/BJ_xilinx/demo_led/Memec_3SLC_VHDL_ISE63/clkdll_divide.vhd \
      EN work/CLKDLL_DIVIDE CP IBUFG      CP CLKDLL         CP BUFG