erg2810_2.rpt

vhdl练习实例。在maxplus2中编写

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  33   (51)  (D)      INPUT               0      0   0    0    0    1    0  A1
  37   (72)  (E)      INPUT               0      0   0    0    0    1    0  A2
  34   (80)  (E)      INPUT               0      0   0    0    0    1    0  B1
  40   (70)  (E)      INPUT               0      0   0    0    0    1    0  B2
  35   (78)  (E)      INPUT               0      0   0    0    0    1    0  C1
  41   (67)  (E)      INPUT               0      0   0    0    0    1    0  C2
  36   (75)  (E)      INPUT               0      0   0    0    0    1    0  D1


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                       e:\max\lianxi\erg2810_2.rpt
erg2810_2

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  44     83    F     OUTPUT      t        0      0   0    7    0    0    0  Y


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                       e:\max\lianxi\erg2810_2.rpt
erg2810_2

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'F':

           Logic cells placed in LAB 'F'
        +- LC83 Y
        | 
        |   Other LABs fed by signals
        |   that feed LAB 'F'
LC      | | A B C D E F G H I J |     Logic cells that feed LAB 'F':

Pin
33   -> * | - - - - - * - - - - | <-- A1
37   -> * | - - - - - * - - - - | <-- A2
34   -> * | - - - - - * - - - - | <-- B1
40   -> * | - - - - - * - - - - | <-- B2
35   -> * | - - - - - * - - - - | <-- C1
41   -> * | - - - - - * - - - - | <-- C2
36   -> * | - - - - - * - - - - | <-- D1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                       e:\max\lianxi\erg2810_2.rpt
erg2810_2

** EQUATIONS **

A1       : INPUT;
A2       : INPUT;
B1       : INPUT;
B2       : INPUT;
C1       : INPUT;
C2       : INPUT;
D1       : INPUT;

-- Node name is 'Y' 
-- Equation name is 'Y', location is LC083, type is output.
 Y       = LCELL( _EQ001 $  VCC);
  _EQ001 = !A1 & !B1 &  C1 &  D1
         # !A2 & !B2
         # !B2 & !C2
         # !A2 & !C2;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                e:\max\lianxi\erg2810_2.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:02
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 7,699K