erg2810_vhd.vhd

来自「vhdl练习实例。在maxplus2中编写」· VHDL 代码 · 共 12 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY erg2810_vhd IS
PORT(
a,b,c : IN STD_LOGIC;
y : OUT STD_LOGIC);
END erg2810_vhd;
ARCHITECTURE vhdl OF erg2810_vhd IS
BEGIN
y<=(a and b) or (b and c) or (a and c);
END vhdl;