halfaddr.vhd

福州大学EDA选修课所有实验课程代码。VHDL语言描述（vhd）

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY halfaddr IS
	PORT(a,b:IN std_logic;
	s,co:OUT std_logic);
END halfaddr;
ARCHITECTURE half1 OF halfaddr IS
SIGNAL c,d:std_logic;
begin
c<=a or b;
d<=a nand b;
co<= not d;
s<=c and d;
end half1;