light_6.vhd

福州大学EDA选修课所有实验课程代码。VHDL语言描述（vhd）

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity light is
	port(clk1:in std_logic;
	light:buffer std_logic_vector(7 downto 0));
end light;
architecture behv of light is
	constant len:integer:=7;
	signal banner:std_logic:='0';
	signal clk,clk2:std_logic;
begin
clk<=(clk1 and banner)or(clk2 and not banner);
process(clk1)
	begin
	if clk1'event and clk1='1' then
	clk2<=not clk2;
	end if;
	end process;
process(clk)
	variable flag:bit_vector(2 downto 0):="000";
	begin
	if clk'event and clk='1' then


	if flag="000" then
	light<='1' & light(len downto 1);
	if light(1)='1' then
	flag:="001";
	end if;

	elsif flag="001" then
	light<=light(len-1 downto 0) & '0';
	if light(6)='0' then
           flag:="010";
	end if;



	elsif flag="010" then
     light<=light(len-2 downto 0)& "11";
	if light(7)='1' then
           flag:="011";
	end if;
    
    elsif flag="011" then
	light<="00" & light(len downto 2) ;
	if light(0)='0' then
           flag:="100";
	end if;



   elsif flag="100" then
        light<=light(len-1 downto 4) &"11"& light(3 downto 1);
     	if light(0)='1' then
           flag:="101";
	end if;
    
    elsif flag="101" then
		light<='0' & light(len downto 5) & light(2 downto 0) & '0' ;
		if light(0)='0' then
           flag:="110";
	end if;



    elsif flag="110" then
        light<=light(len-1 downto 6) &'1'&'1'& light(5 downto 1);
	if light(0)='1' then
           flag:="111";
	end if;
    elsif flag="111" then
	banner<=not banner;
    light<="00000000";
	flag:="000";

	end if;
end if;
end process;
end behv;