tosin.vhd

福州大学EDA选修课所有实验课程代码。VHDL语言描述（vhd）

library ieee;
use ieee.std_logic_1164.all;
entity tosin is
port(clk:in std_logic;
		cs,wr: out std_logic;
	dispdata: out integer range 255 downto 0);
end tosin;
architecture da of tosin is
	signal q :integer range 63 downto 0;
	signal d :integer range 255 downto 0;
begin
	process(clk)
	begin
	if (clk'event and clk='1') 
		then 
			cs <= '0';
			wr <= '0';
			q <=q+1;
		end if;
	end process;

	process(q)
	begin
		case q is
		when 00=> d<=255;when 01=> d<=254;when 02=> d<=252;
		when 03=> d<=248;when 04=> d<=243;when 05=> d<=237;
		when 06=> d<=230;when 07=> d<=222;when 08=> d<=213;
		when 09=> d<=204;when 10=> d<=193;when 11=> d<=182;
		when 12=> d<=171;when 13=> d<=159;when 14=> d<=146;
		when 15=> d<=134;when 16=> d<=121;when 17=> d<=109;
		when 18=> d<=96; when 19=> d<=84; when 20=> d<=73;
		when 21=> d<=62; when 22=> d<=51; when 23=> d<=42;
		when 24=> d<=33; when 25=> d<=25; when 26=> d<=18;
		when 27=> d<=12; when 28=> d<=7;  when 29=> d<=3;
		when 30=> d<=1;  when 31=> d<=0;  when 32=> d<=0;
		when 33=> d<=1;  when 34=> d<=3;  when 35=> d<=7;
		when 36=> d<=12; when 37=> d<=18; when 38=> d<=25;
		when 39=> d<=33; when 40=> d<=42; when 41=> d<=51;
		when 42=> d<=62; when 43=> d<=73; when 44=> d<=84;
		when 45=> d<=96; when 46=> d<=109;when 47=> d<=121;
		when 48=> d<=134;when 49=> d<=146;when 50=> d<=159;
		when 51=> d<=171;when 52=> d<=182;when 53=> d<=193;
		when 54=> d<=204;when 55=> d<=213;when 56=> d<=222;
		when 57=> d<=230;when 58=> d<=237;when 59=> d<=243;
		when 60=> d<=248;when 61=> d<=252;when 62=> d<=254;
		when 63=> d<=255;
		when others=>null;
		end case;
	end process;
	dispdata<=d;
end da;