📄 zhankong.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity zhankong is
port
(clk,clkin:in std_logic;
beichu1,beichu2,beichu3,chu1,chu2,chu3:out Integer range 0 to 9
);
end;
architecture a of zhankong is
signal En,High,m,n,Entransfer:std_logic;
signal Highnum1,Highnum2,Highnum3,Totalnum1,Totalnum2,Totalnum3: Integer range 0 to 9;
begin
process(clkin)
begin
if rising_edge(clkin) then
En<=not En; --En?clkin????
m<=not m; --High='1'??????????
end if;
end process;
process(clkin)
begin
if falling_edge(clkin) then
n<=not n; --High='0'??????????
end if;
end process;
High<=m xor n;
process(clk)
begin
if rising_edge(clk) then
if En='1' then --En='1'?????
if Entransfer='1' then --Entransfer='1'????????
Entransfer<='0';
beichu1<=Highnum1;
beichu2<=Highnum2;
beichu3<=Highnum3;
chu1<=Totalnum1;
chu2<=Totalnum2;
chu3<=Totalnum3;
Highnum1<=0;
Highnum2<=0;
Highnum3<=0; --??????????????
Totalnum1<=0;
Totalnum2<=0;
Totalnum3<=0;
end if;
else Entransfer<='1'; --En='0'?????
if Totalnum1=9 then
if Totalnum2=9 then
if Totalnum3=9 then
null;
else
Totalnum3<=Totalnum3+1;
Totalnum2<=0;
Totalnum1<=0;
end if;
else
Totalnum2<=Totalnum2+1;
Totalnum1<=0;
end if;
else
Totalnum1<=Totalnum1+1;
--Totalnum<=Totalnum+1;
end if;
if High='1' then
if Highnum1=9 then
if Highnum2=9 then
if Highnum3=9 then
null;
else
Highnum3<=Highnum3+1;
Highnum2<=0;
Highnum1<=0;
end if;
else
Highnum2<=Highnum2+1;
Highnum1<=0;
end if;
else
Highnum1<=Highnum1+1;
--Totalnum<=Totalnum+1;
end if;
-- Highnum<=Highnum+1;
end if;
end if;
end if;
end process;
end a;
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