📄 data_pro.rpt
字号:
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\vhdl\vhd\data_pro.rpt
data_pro
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - B 13 DFFE + 0 3 0 6 counter2 (:47)
- 3 - B 13 DFFE + 0 2 0 7 counter1 (:48)
- 8 - B 18 DFFE + 0 1 0 8 counter0 (:49)
- 1 - B 13 OR2 ! 0 3 0 11 :84
- 8 - B 13 AND2 0 3 0 8 :488
- 2 - B 18 OR2 1 3 0 1 :491
- 7 - B 13 AND2 0 3 0 8 :498
- 6 - B 13 AND2 0 3 0 8 :508
- 8 - B 15 OR2 1 3 0 1 :511
- 4 - B 13 AND2 0 3 0 8 :518
- 2 - B 13 AND2 0 3 0 8 :528
- 3 - B 15 OR2 1 3 1 1 :531
- 3 - B 18 OR2 1 3 0 1 :540
- 8 - B 14 OR2 1 3 0 1 :546
- 5 - B 14 OR2 1 3 1 1 :552
- 4 - B 18 OR2 1 3 0 1 :561
- 6 - B 20 OR2 1 3 0 1 :567
- 7 - B 20 OR2 1 3 1 1 :573
- 5 - B 18 OR2 1 3 0 1 :582
- 6 - B 18 OR2 1 3 0 1 :588
- 1 - B 18 OR2 1 3 1 1 :594
- 2 - B 15 OR2 1 2 0 1 :600
- 4 - B 15 OR2 1 2 0 1 :603
- 5 - B 15 OR2 1 2 0 1 :606
- 6 - B 15 OR2 1 2 0 1 :609
- 7 - B 15 OR2 1 2 0 1 :612
- 1 - B 15 OR2 1 2 1 1 :615
- 1 - B 20 OR2 1 2 0 1 :621
- 2 - B 20 OR2 1 2 0 1 :624
- 3 - B 20 OR2 1 2 0 1 :627
- 4 - B 20 OR2 1 2 0 1 :630
- 5 - B 20 OR2 1 2 0 1 :633
- 8 - B 20 OR2 1 2 1 1 :636
- 1 - B 14 OR2 1 2 0 1 :642
- 3 - B 14 OR2 1 2 0 1 :645
- 4 - B 14 OR2 1 2 0 1 :648
- 6 - B 14 OR2 1 2 0 1 :651
- 7 - B 14 OR2 1 2 0 1 :654
- 2 - B 14 OR2 1 2 1 1 :657
- 1 - B 17 OR2 1 2 0 1 :663
- 2 - B 17 OR2 1 2 0 1 :666
- 3 - B 17 OR2 1 2 0 1 :669
- 4 - B 17 OR2 1 2 0 1 :672
- 5 - B 17 OR2 1 2 0 1 :675
- 7 - B 17 OR2 1 2 1 1 :678
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\vhdl\vhd\data_pro.rpt
data_pro
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 3/ 48( 6%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
B: 26/ 96( 27%) 0/ 48( 0%) 20/ 48( 41%) 6/16( 37%) 3/16( 18%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\vhdl\vhd\data_pro.rpt
data_pro
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 3 clk
Device-Specific Information: d:\vhdl\vhd\data_pro.rpt
data_pro
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 3 enable
Device-Specific Information: d:\vhdl\vhd\data_pro.rpt
data_pro
** EQUATIONS **
beichu10 : INPUT;
beichu11 : INPUT;
beichu12 : INPUT;
beichu13 : INPUT;
beichu20 : INPUT;
beichu21 : INPUT;
beichu22 : INPUT;
beichu23 : INPUT;
beichu30 : INPUT;
beichu31 : INPUT;
beichu32 : INPUT;
beichu33 : INPUT;
chu10 : INPUT;
chu11 : INPUT;
chu12 : INPUT;
chu13 : INPUT;
chu20 : INPUT;
chu21 : INPUT;
chu22 : INPUT;
chu23 : INPUT;
chu30 : INPUT;
chu31 : INPUT;
chu32 : INPUT;
chu33 : INPUT;
clk : INPUT;
enable : INPUT;
Numf10 : INPUT;
Numf11 : INPUT;
Numf12 : INPUT;
Numf13 : INPUT;
Numf20 : INPUT;
Numf21 : INPUT;
Numf22 : INPUT;
Numf23 : INPUT;
Numf30 : INPUT;
Numf31 : INPUT;
Numf32 : INPUT;
Numf33 : INPUT;
-- Node name is ':49' = 'counter0'
-- Equation name is 'counter0', location is LC8_B18, type is buried.
counter0 = DFFE( _EQ001, GLOBAL( clk), GLOBAL( enable), VCC, VCC);
_EQ001 = !counter0 & !_LC1_B13;
-- Node name is ':48' = 'counter1'
-- Equation name is 'counter1', location is LC3_B13, type is buried.
counter1 = DFFE( _EQ002, GLOBAL( clk), GLOBAL( enable), VCC, VCC);
_EQ002 = counter0 & !counter1 & !_LC1_B13
# !counter0 & counter1 & !_LC1_B13;
-- Node name is ':47' = 'counter2'
-- Equation name is 'counter2', location is LC5_B13, type is buried.
counter2 = DFFE( _EQ003, GLOBAL( clk), GLOBAL( enable), VCC, VCC);
_EQ003 = !counter0 & counter2 & !_LC1_B13
# !counter1 & counter2 & !_LC1_B13
# counter0 & counter1 & !counter2 & !_LC1_B13;
-- Node name is 'data0'
-- Equation name is 'data0', type is output
data0 = _LC7_B17;
-- Node name is 'data1'
-- Equation name is 'data1', type is output
data1 = _LC2_B14;
-- Node name is 'data2'
-- Equation name is 'data2', type is output
data2 = _LC8_B20;
-- Node name is 'data3'
-- Equation name is 'data3', type is output
data3 = _LC1_B15;
-- Node name is 'data4'
-- Equation name is 'data4', type is output
data4 = _LC1_B18;
-- Node name is 'data5'
-- Equation name is 'data5', type is output
data5 = _LC7_B20;
-- Node name is 'data6'
-- Equation name is 'data6', type is output
data6 = _LC5_B14;
-- Node name is 'data7'
-- Equation name is 'data7', type is output
data7 = _LC3_B15;
-- Node name is ':84'
-- Equation name is '_LC1_B13', type is buried
!_LC1_B13 = _LC1_B13~NOT;
_LC1_B13~NOT = LCELL( _EQ004);
_EQ004 = !counter2
# counter0
# !counter1;
-- Node name is ':488'
-- Equation name is '_LC8_B13', type is buried
_LC8_B13 = LCELL( _EQ005);
_EQ005 = counter0 & !counter1 & counter2;
-- Node name is ':491'
-- Equation name is '_LC2_B18', type is buried
_LC2_B18 = LCELL( _EQ006);
_EQ006 = !_LC1_B13 & _LC3_B15 & !_LC8_B13
# chu23 & _LC8_B13;
-- Node name is ':498'
-- Equation name is '_LC7_B13', type is buried
_LC7_B13 = LCELL( _EQ007);
_EQ007 = !counter0 & !counter1 & counter2;
-- Node name is ':508'
-- Equation name is '_LC6_B13', type is buried
_LC6_B13 = LCELL( _EQ008);
_EQ008 = counter0 & counter1 & !counter2;
-- Node name is ':511'
-- Equation name is '_LC8_B15', type is buried
_LC8_B15 = LCELL( _EQ009);
_EQ009 = _LC2_B18 & !_LC6_B13 & !_LC7_B13
# beichu23 & _LC6_B13;
-- Node name is ':518'
-- Equation name is '_LC4_B13', type is buried
_LC4_B13 = LCELL( _EQ010);
_EQ010 = !counter0 & counter1 & !counter2;
-- Node name is ':528'
-- Equation name is '_LC2_B13', type is buried
_LC2_B13 = LCELL( _EQ011);
_EQ011 = counter0 & !counter1 & !counter2;
-- Node name is ':531'
-- Equation name is '_LC3_B15', type is buried
_LC3_B15 = LCELL( _EQ012);
_EQ012 = !_LC2_B13 & !_LC4_B13 & _LC8_B15
# _LC2_B13 & Numf23;
-- Node name is ':540'
-- Equation name is '_LC3_B18', type is buried
_LC3_B18 = LCELL( _EQ013);
_EQ013 = !_LC1_B13 & _LC5_B14 & !_LC8_B13
# chu22 & _LC8_B13;
-- Node name is ':546'
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