📄 data_pro.rpt
字号:
Project Information d:\vhdl\vhd\data_pro.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 11/25/2005 18:08:15
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
DATA_PRO
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
data_pro EPF10K10LC84-3 38 8 0 0 0 % 45 7 %
User Pins: 38 8 0
Project Information d:\vhdl\vhd\data_pro.rpt
** FILE HIERARCHY **
|lpm_add_sub:107|
|lpm_add_sub:107|addcore:adder|
|lpm_add_sub:107|altshift:result_ext_latency_ffs|
|lpm_add_sub:107|altshift:carry_ext_latency_ffs|
|lpm_add_sub:107|altshift:oflow_ext_latency_ffs|
Device-Specific Information: d:\vhdl\vhd\data_pro.rpt
data_pro
***** Logic for device 'data_pro' compiled without errors.
Device: EPF10K10LC84-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
^
C
b b b b b b b O
e e e e e e e N
i i i i V N e i i G N i N F
c c c c c c c C u n c c N u c u c _ ^
h h h h h h h C m a h h D m h m h # D n
u u u u u u u I f b c u u I f u f u T O C
2 1 3 2 2 1 1 N 1 l l 3 2 N 1 3 2 2 C N E
3 2 1 1 2 1 2 T 1 e k 0 0 T 2 2 1 2 K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | data4
^nCE | 14 72 | data1
#TDI | 15 71 | RESERVED
RESERVED | 16 70 | data2
RESERVED | 17 69 | RESERVED
RESERVED | 18 68 | GNDINT
RESERVED | 19 67 | beichu23
VCCINT | 20 66 | data7
Numf10 | 21 65 | data6
beichu33 | 22 EPF10K10LC84-3 64 | data5
Numf20 | 23 63 | VCCINT
Numf30 | 24 62 | data3
Numf31 | 25 61 | RESERVED
GNDINT | 26 60 | RESERVED
RESERVED | 27 59 | RESERVED
RESERVED | 28 58 | data0
RESERVED | 29 57 | #TMS
RESERVED | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | chu31
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ c c b N N V G c b c V G N c c N c b N
C n h h e u u C N h e h C N u h h u h e u
C C u u i m m C D u i u C D m u u m u i m
I O 1 2 c f f I I 3 c 1 I I f 3 2 f 3 c f
N N 3 1 h 3 2 N N 0 h 0 N N 1 3 0 3 2 h 2
T F u 2 3 T T u T T 3 3 u 2
I 1 1 1
G 1 0 3
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\vhdl\vhd\data_pro.rpt
data_pro
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
B13 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 1/2 1/22( 4%)
B14 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 15/22( 68%)
B15 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 15/22( 68%)
B17 6/ 8( 75%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 12/22( 54%)
B18 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 1/2 1/2 15/22( 68%)
B20 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 15/22( 68%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 40/53 ( 75%)
Total logic cells used: 45/576 ( 7%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.26/4 ( 81%)
Total fan-in: 147/2304 ( 6%)
Total input pins required: 38
Total input I/O cell registers required: 0
Total output pins required: 8
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 45
Total flipflops required: 3
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 0/ 576 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 8 8 8 0 6 7 0 8 0 0 0 0 45/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 0 0 0 0 0 0 0 0 0 0 0 0 8 8 8 0 6 7 0 8 0 0 0 0 45/0
Device-Specific Information: d:\vhdl\vhd\data_pro.rpt
data_pro
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
43 - - - -- INPUT 0 0 0 1 beichu10
37 - - - 09 INPUT 0 0 0 1 beichu11
5 - - - 05 INPUT 0 0 0 1 beichu12
52 - - - 19 INPUT 0 0 0 1 beichu13
83 - - - 13 INPUT 0 0 0 1 beichu20
8 - - - 03 INPUT 0 0 0 1 beichu21
7 - - - 03 INPUT 0 0 0 1 beichu22
67 - - B -- INPUT 0 0 0 1 beichu23
84 - - - -- INPUT 0 0 0 1 beichu30
9 - - - 02 INPUT 0 0 0 1 beichu31
80 - - - 23 INPUT 0 0 0 1 beichu32
22 - - B -- INPUT 0 0 0 1 beichu33
44 - - - -- INPUT 0 0 0 1 chu10
6 - - - 04 INPUT 0 0 0 1 chu11
10 - - - 01 INPUT 0 0 0 1 chu12
35 - - - 06 INPUT 0 0 0 1 chu13
49 - - - 16 INPUT 0 0 0 1 chu20
36 - - - 07 INPUT 0 0 0 1 chu21
78 - - - 24 INPUT 0 0 0 1 chu22
11 - - - 01 INPUT 0 0 0 1 chu23
42 - - - -- INPUT 0 0 0 1 chu30
54 - - - 21 INPUT 0 0 0 1 chu31
51 - - - 18 INPUT 0 0 0 1 chu32
48 - - - 15 INPUT 0 0 0 1 chu33
1 - - - -- INPUT G 0 0 0 0 clk
2 - - - -- INPUT G 0 0 0 0 enable
21 - - B -- INPUT 0 0 0 1 Numf10
3 - - - 12 INPUT 0 0 0 1 Numf11
81 - - - 22 INPUT 0 0 0 1 Numf12
47 - - - 14 INPUT 0 0 0 1 Numf13
23 - - B -- INPUT 0 0 0 1 Numf20
79 - - - 24 INPUT 0 0 0 1 Numf21
53 - - - 20 INPUT 0 0 0 1 Numf22
39 - - - 11 INPUT 0 0 0 1 Numf23
24 - - B -- INPUT 0 0 0 1 Numf30
25 - - B -- INPUT 0 0 0 1 Numf31
38 - - - 10 INPUT 0 0 0 1 Numf32
50 - - - 17 INPUT 0 0 0 1 Numf33
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\vhdl\vhd\data_pro.rpt
data_pro
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
58 - - C -- OUTPUT 0 1 0 0 data0
72 - - A -- OUTPUT 0 1 0 0 data1
70 - - A -- OUTPUT 0 1 0 0 data2
62 - - C -- OUTPUT 0 1 0 0 data3
73 - - A -- OUTPUT 0 1 0 0 data4
64 - - B -- OUTPUT 0 1 0 0 data5
65 - - B -- OUTPUT 0 1 0 0 data6
66 - - B -- OUTPUT 0 1 0 0 data7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -