baseclk.vhd

来自「本频率计具有测周、测频、测量占空比等基本功能」· VHDL 代码 · 共 23 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity baseclk is
port
( clk1M,clk100k:in std_logic;
  period:in std_logic;
  clk:out std_logic
);
end;

architecture a of baseclk is
begin
process(clk1M,clk100k,period)
begin
  if(period='1') then
    clk<=clk100k;
    else clk<=clk1M;
  end if;
end process;
end a;