fredevider.rpt
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RPT
623 行
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 1/ 96( 1%) 0/ 48( 0%) 4/ 48( 8%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\maxplus2\vhd\fredevider.rpt
fredevider
** CLOCK SIGNALS **
Type Fan-out Name
DFF 6 Temp2
DFF 6 Temp3
DFF 6 Temp4
DFF 6 Temp5
INPUT 4 clock
Device-Specific Information: f:\maxplus2\vhd\fredevider.rpt
fredevider
** EQUATIONS **
clock : INPUT;
-- Node name is 'clk1KHz'
-- Equation name is 'clk1KHz', type is output
clk1KHz = Temp3;
-- Node name is 'clk10Hz'
-- Equation name is 'clk10Hz', type is output
clk10Hz = Temp1;
-- Node name is 'clk10KHz'
-- Equation name is 'clk10KHz', type is output
clk10KHz = Temp4;
-- Node name is 'clk100Hz'
-- Equation name is 'clk100Hz', type is output
clk100Hz = Temp2;
-- Node name is 'clk100KHz'
-- Equation name is 'clk100KHz', type is output
clk100KHz = Temp5;
-- Node name is ':10' = 'Counter10'
-- Equation name is 'Counter10', location is LC8_B20, type is buried.
Counter10 = DFFE( _EQ001, Temp2, VCC, VCC, VCC);
_EQ001 = !Counter10 & Counter11
# !Counter10 & !Counter12;
-- Node name is ':9' = 'Counter11'
-- Equation name is 'Counter11', location is LC5_B20, type is buried.
Counter11 = DFFE( _EQ002, Temp2, VCC, VCC, VCC);
_EQ002 = Counter10 & !Counter11
# !Counter10 & Counter11;
-- Node name is ':8' = 'Counter12'
-- Equation name is 'Counter12', location is LC7_B20, type is buried.
Counter12 = DFFE( _EQ003, Temp2, VCC, VCC, VCC);
_EQ003 = Counter10 & Counter11 & !Counter12
# !Counter10 & Counter11 & Counter12
# Counter10 & !Counter11 & Counter12;
-- Node name is ':15' = 'Counter20'
-- Equation name is 'Counter20', location is LC4_B20, type is buried.
Counter20 = DFFE( _EQ004, Temp3, VCC, VCC, VCC);
_EQ004 = !Counter20 & Counter21
# !Counter20 & !Counter22;
-- Node name is ':14' = 'Counter21'
-- Equation name is 'Counter21', location is LC1_B20, type is buried.
Counter21 = DFFE( _EQ005, Temp3, VCC, VCC, VCC);
_EQ005 = Counter20 & !Counter21
# !Counter20 & Counter21;
-- Node name is ':13' = 'Counter22'
-- Equation name is 'Counter22', location is LC3_B20, type is buried.
Counter22 = DFFE( _EQ006, Temp3, VCC, VCC, VCC);
_EQ006 = Counter20 & Counter21 & !Counter22
# !Counter20 & Counter21 & Counter22
# Counter20 & !Counter21 & Counter22;
-- Node name is ':19' = 'Counter30'
-- Equation name is 'Counter30', location is LC8_B21, type is buried.
Counter30 = DFFE( _EQ007, Temp4, VCC, VCC, VCC);
_EQ007 = !Counter30 & Counter31
# !Counter30 & !Counter32;
-- Node name is ':18' = 'Counter31'
-- Equation name is 'Counter31', location is LC6_B21, type is buried.
Counter31 = DFFE( _EQ008, Temp4, VCC, VCC, VCC);
_EQ008 = Counter30 & !Counter31
# !Counter30 & Counter31;
-- Node name is ':17' = 'Counter32'
-- Equation name is 'Counter32', location is LC7_B21, type is buried.
Counter32 = DFFE( _EQ009, Temp4, VCC, VCC, VCC);
_EQ009 = Counter30 & Counter31 & !Counter32
# !Counter30 & Counter31 & Counter32
# Counter30 & !Counter31 & Counter32;
-- Node name is ':23' = 'Counter40'
-- Equation name is 'Counter40', location is LC4_B21, type is buried.
Counter40 = DFFE( _EQ010, Temp5, VCC, VCC, VCC);
_EQ010 = !Counter40 & Counter41
# !Counter40 & !Counter42;
-- Node name is ':22' = 'Counter41'
-- Equation name is 'Counter41', location is LC2_B21, type is buried.
Counter41 = DFFE( _EQ011, Temp5, VCC, VCC, VCC);
_EQ011 = Counter40 & !Counter41
# !Counter40 & Counter41;
-- Node name is ':21' = 'Counter42'
-- Equation name is 'Counter42', location is LC3_B21, type is buried.
Counter42 = DFFE( _EQ012, Temp5, VCC, VCC, VCC);
_EQ012 = Counter40 & Counter41 & !Counter42
# !Counter40 & Counter41 & Counter42
# Counter40 & !Counter41 & Counter42;
-- Node name is ':26' = 'Counter50'
-- Equation name is 'Counter50', location is LC3_B22, type is buried.
Counter50 = DFFE( _EQ013, GLOBAL( clock), VCC, VCC, VCC);
_EQ013 = !Counter50 & Counter51
# !Counter50 & !Counter52;
-- Node name is ':25' = 'Counter51'
-- Equation name is 'Counter51', location is LC1_B22, type is buried.
Counter51 = DFFE( _EQ014, GLOBAL( clock), VCC, VCC, VCC);
_EQ014 = Counter50 & !Counter51
# !Counter50 & Counter51;
-- Node name is ':24' = 'Counter52'
-- Equation name is 'Counter52', location is LC2_B22, type is buried.
Counter52 = DFFE( _EQ015, GLOBAL( clock), VCC, VCC, VCC);
_EQ015 = Counter50 & Counter51 & !Counter52
# !Counter50 & Counter51 & Counter52
# Counter50 & !Counter51 & Counter52;
-- Node name is ':11' = 'Temp1'
-- Equation name is 'Temp1', location is LC2_B20, type is buried.
Temp1 = DFFE( _EQ016, Temp2, VCC, VCC, VCC);
_EQ016 = Counter11 & Temp1
# !Counter12 & Temp1
# Counter10 & Temp1
# !Counter10 & !Counter11 & Counter12 & !Temp1;
-- Node name is ':7' = 'Temp2'
-- Equation name is 'Temp2', location is LC6_B20, type is buried.
Temp2 = DFFE( _EQ017, Temp3, VCC, VCC, VCC);
_EQ017 = Counter21 & Temp2
# !Counter22 & Temp2
# Counter20 & Temp2
# !Counter20 & !Counter21 & Counter22 & !Temp2;
-- Node name is ':12' = 'Temp3'
-- Equation name is 'Temp3', location is LC5_B21, type is buried.
Temp3 = DFFE( _EQ018, Temp4, VCC, VCC, VCC);
_EQ018 = Counter31 & Temp3
# !Counter32 & Temp3
# Counter30 & Temp3
# !Counter30 & !Counter31 & Counter32 & !Temp3;
-- Node name is ':16' = 'Temp4'
-- Equation name is 'Temp4', location is LC1_B21, type is buried.
Temp4 = DFFE( _EQ019, Temp5, VCC, VCC, VCC);
_EQ019 = Counter41 & Temp4
# !Counter42 & Temp4
# Counter40 & Temp4
# !Counter40 & !Counter41 & Counter42 & !Temp4;
-- Node name is ':20' = 'Temp5'
-- Equation name is 'Temp5', location is LC7_B22, type is buried.
Temp5 = DFFE( _EQ020, GLOBAL( clock), VCC, VCC, VCC);
_EQ020 = Counter51 & Temp5
# !Counter52 & Temp5
# Counter50 & Temp5
# !Counter50 & !Counter51 & Counter52 & !Temp5;
Project Information f:\maxplus2\vhd\fredevider.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,919K
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