numlatch.rpt
来自「本频率计具有测周、测频、测量占空比等基本功能」· RPT 代码 · 共 574 行 · 第 1/2 页
RPT
574 行
numlatch
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 8/ 96( 8%) 3/ 48( 6%) 0/ 48( 0%) 3/16( 18%) 6/16( 37%) 0/16( 0%)
C: 4/ 96( 4%) 0/ 48( 0%) 3/ 48( 6%) 3/16( 18%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\vhd\numlatch.rpt
numlatch
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 12 clock
Device-Specific Information: d:\vhd\numlatch.rpt
numlatch
** EQUATIONS **
clock : INPUT;
en : INPUT;
numina0 : INPUT;
numina1 : INPUT;
numina2 : INPUT;
numina3 : INPUT;
numinb0 : INPUT;
numinb1 : INPUT;
numinb2 : INPUT;
numinb3 : INPUT;
numinc0 : INPUT;
numinc1 : INPUT;
numinc2 : INPUT;
numinc3 : INPUT;
-- Node name is ':30' = 'm10'
-- Equation name is 'm10', location is LC4_C21, type is buried.
m10 = DFFE( _EQ001, GLOBAL( clock), VCC, VCC, VCC);
_EQ001 = !en & m10
# en & numina0;
-- Node name is ':29' = 'm11'
-- Equation name is 'm11', location is LC1_C21, type is buried.
m11 = DFFE( _EQ002, GLOBAL( clock), VCC, VCC, VCC);
_EQ002 = !en & m11
# en & numina1;
-- Node name is ':28' = 'm12'
-- Equation name is 'm12', location is LC6_B12, type is buried.
m12 = DFFE( _EQ003, GLOBAL( clock), VCC, VCC, VCC);
_EQ003 = !en & m12
# en & numina2;
-- Node name is ':27' = 'm13'
-- Equation name is 'm13', location is LC7_B12, type is buried.
m13 = DFFE( _EQ004, GLOBAL( clock), VCC, VCC, VCC);
_EQ004 = !en & m13
# en & numina3;
-- Node name is ':34' = 'm20'
-- Equation name is 'm20', location is LC4_B12, type is buried.
m20 = DFFE( _EQ005, GLOBAL( clock), VCC, VCC, VCC);
_EQ005 = !en & m20
# en & numinb0;
-- Node name is ':33' = 'm21'
-- Equation name is 'm21', location is LC3_C21, type is buried.
m21 = DFFE( _EQ006, GLOBAL( clock), VCC, VCC, VCC);
_EQ006 = !en & m21
# en & numinb1;
-- Node name is ':32' = 'm22'
-- Equation name is 'm22', location is LC1_B12, type is buried.
m22 = DFFE( _EQ007, GLOBAL( clock), VCC, VCC, VCC);
_EQ007 = !en & m22
# en & numinb2;
-- Node name is ':31' = 'm23'
-- Equation name is 'm23', location is LC3_B12, type is buried.
m23 = DFFE( _EQ008, GLOBAL( clock), VCC, VCC, VCC);
_EQ008 = !en & m23
# en & numinb3;
-- Node name is ':38' = 'm30'
-- Equation name is 'm30', location is LC8_B12, type is buried.
m30 = DFFE( _EQ009, GLOBAL( clock), VCC, VCC, VCC);
_EQ009 = !en & m30
# en & numinc0;
-- Node name is ':37' = 'm31'
-- Equation name is 'm31', location is LC2_B12, type is buried.
m31 = DFFE( _EQ010, GLOBAL( clock), VCC, VCC, VCC);
_EQ010 = !en & m31
# en & numinc1;
-- Node name is ':36' = 'm32'
-- Equation name is 'm32', location is LC5_B12, type is buried.
m32 = DFFE( _EQ011, GLOBAL( clock), VCC, VCC, VCC);
_EQ011 = !en & m32
# en & numinc2;
-- Node name is ':35' = 'm33'
-- Equation name is 'm33', location is LC5_C21, type is buried.
m33 = DFFE( _EQ012, GLOBAL( clock), VCC, VCC, VCC);
_EQ012 = !en & m33
# en & numinc3;
-- Node name is 'numouta0'
-- Equation name is 'numouta0', type is output
numouta0 = m10;
-- Node name is 'numouta1'
-- Equation name is 'numouta1', type is output
numouta1 = m11;
-- Node name is 'numouta2'
-- Equation name is 'numouta2', type is output
numouta2 = m12;
-- Node name is 'numouta3'
-- Equation name is 'numouta3', type is output
numouta3 = m13;
-- Node name is 'numoutb0'
-- Equation name is 'numoutb0', type is output
numoutb0 = m20;
-- Node name is 'numoutb1'
-- Equation name is 'numoutb1', type is output
numoutb1 = m21;
-- Node name is 'numoutb2'
-- Equation name is 'numoutb2', type is output
numoutb2 = m22;
-- Node name is 'numoutb3'
-- Equation name is 'numoutb3', type is output
numoutb3 = m23;
-- Node name is 'numoutc0'
-- Equation name is 'numoutc0', type is output
numoutc0 = m30;
-- Node name is 'numoutc1'
-- Equation name is 'numoutc1', type is output
numoutc1 = m31;
-- Node name is 'numoutc2'
-- Equation name is 'numoutc2', type is output
numoutc2 = m32;
-- Node name is 'numoutc3'
-- Equation name is 'numoutc3', type is output
numoutc3 = m33;
Project Information d:\vhd\numlatch.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 30,543K
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?