numlatch.vhd

来自「本频率计具有测周、测频、测量占空比等基本功能」· VHDL 代码 · 共 34 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity Numlatch is
port
(clock,en:in std_logic;
 numina:in std_logic_vector(3 downto 0);
 numinb:in std_logic_vector(3 downto 0);
 numinc:in std_logic_vector(3 downto 0);
 numouta:out std_logic_vector(3 downto 0);
 numoutb:out std_logic_vector(3 downto 0);
 numoutc:out std_logic_vector(3 downto 0)
);
end;

architecture a of Numlatch is
signal m1,m2,m3:std_logic_vector(3 downto 0);
begin
 process(clock)
 begin
  if rising_edge(clock) then
    if en='1' then
    m1<=numina;
    m2<=numinb;
    m3<=numinc;
  end if;
end if;
 end process;
    numouta<=m1;
    numoutb<=m2;
    numoutc<=m3;
 end a;