divider.hier_info

这个是用vhdl语言编写的除法器,仅仅供大家参考.

|divider
dividend[0] => remainder~34.DATAB
dividend[1] => remainder~33.DATAB
dividend[2] => remainder~32.DATAB
dividend[3] => remainder~31.DATAB
divisor[0] => drreg[0].DATAIN
divisor[1] => drreg[1].DATAIN
divisor[2] => drreg[2].DATAIN
divisor[3] => drreg[3].DATAIN
clock => drreg[2].CLK
clock => drreg[1].CLK
clock => drreg[0].CLK
clock => remainder[8]~reg0.CLK
clock => remainder[7]~reg0.CLK
clock => remainder[6]~reg0.CLK
clock => remainder[5]~reg0.CLK
clock => remainder[4]~reg0.CLK
clock => remainder[3]~reg0.CLK
clock => remainder[2]~reg0.CLK
clock => remainder[1]~reg0.CLK
clock => remainder[0]~reg0.CLK
clock => count[1].CLK
clock => count[0].CLK
clock => count2[1].CLK
clock => count2[0].CLK
clock => finish~reg0.CLK
clock => drreg[3].CLK
quotient[0] <= quotient~3.DB_MAX_OUTPUT_PORT_TYPE
quotient[1] <= quotient~2.DB_MAX_OUTPUT_PORT_TYPE
quotient[2] <= quotient~1.DB_MAX_OUTPUT_PORT_TYPE
quotient[3] <= quotient~0.DB_MAX_OUTPUT_PORT_TYPE
remainder_r[0] <= remainder_r~2.DB_MAX_OUTPUT_PORT_TYPE
remainder_r[1] <= remainder_r~1.DB_MAX_OUTPUT_PORT_TYPE
remainder_r[2] <= remainder_r~0.DB_MAX_OUTPUT_PORT_TYPE
remainder_r[3] <= <GND>
remainder[0] <= remainder[0]~reg0
remainder[1] <= remainder[1]~reg0
remainder[2] <= remainder[2]~reg0
remainder[3] <= remainder[3]~reg0
remainder[4] <= remainder[4]~reg0
remainder[5] <= remainder[5]~reg0
remainder[6] <= remainder[6]~reg0
remainder[7] <= remainder[7]~reg0
remainder[8] <= remainder[8]~reg0
finish <= finish~reg0