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📄 divider.tan.qmsg

📁 这个是用vhdl语言编写的除法器,仅仅供大家参考.
💻 QMSG
📖 第 1 页 / 共 4 页
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1234 
{ "Info" "ITDB_FULL_TCO_RESULT" "clock quotient\[1\] finish~reg0 18.400 ns register " "Info: tco from clock \"clock\" to destination pin \"quotient\[1\]\" through register \"finish~reg0\" is 18.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 1.900 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clock 1 CLK PIN_79 18 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 18; CLK Node = 'clock'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "" { clock } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns finish~reg0 2 REG LC4_J38 8 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC4_J38; Fanout = 8; REG Node = 'finish~reg0'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "1.400 ns" { clock finish~reg0 } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 90 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns 26.32 % " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 73.68 % " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "1.900 ns" { clock finish~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out finish~reg0 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 90 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "15.400 ns + Longest register pin " "Info: + Longest register to pin delay is 15.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns finish~reg0 1 REG LC4_J38 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_J38; Fanout = 8; REG Node = 'finish~reg0'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "" { finish~reg0 } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 90 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.900 ns) 3.700 ns quotient~42 2 COMB LC2_J43 1 " "Info: 2: + IC(1.800 ns) + CELL(1.900 ns) = 3.700 ns; Loc. = LC2_J43; Fanout = 1; COMB Node = 'quotient~42'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "3.700 ns" { finish~reg0 quotient~42 } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(8.600 ns) 15.400 ns quotient\[1\] 3 PIN PIN_8 0 " "Info: 3: + IC(3.100 ns) + CELL(8.600 ns) = 15.400 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'quotient\[1\]'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "11.700 ns" { quotient~42 quotient[1] } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.500 ns 68.18 % " "Info: Total cell delay = 10.500 ns ( 68.18 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.900 ns 31.82 % " "Info: Total interconnect delay = 4.900 ns ( 31.82 % )" {  } {  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "15.400 ns" { finish~reg0 quotient~42 quotient[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "15.400 ns" { finish~reg0 quotient~42 quotient[1] } { 0.000ns 1.800ns 3.100ns } { 0.000ns 1.900ns 8.600ns } } }  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "1.900 ns" { clock finish~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out finish~reg0 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "15.400 ns" { finish~reg0 quotient~42 quotient[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "15.400 ns" { finish~reg0 quotient~42 quotient[1] } { 0.000ns 1.800ns 3.100ns } { 0.000ns 1.900ns 8.600ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "remainder\[4\]~reg0 dividend\[3\] clock -4.900 ns register " "Info: th for register \"remainder\[4\]~reg0\" (data pin = \"dividend\[3\]\", clock pin = \"clock\") is -4.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 1.900 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clock 1 CLK PIN_79 18 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 18; CLK Node = 'clock'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "" { clock } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns remainder\[4\]~reg0 2 REG LC5_J40 5 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC5_J40; Fanout = 5; REG Node = 'remainder\[4\]~reg0'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "1.400 ns" { clock remainder[4]~reg0 } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 64 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns 26.32 % " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 73.68 % " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "1.900 ns" { clock remainder[4]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out remainder[4]~reg0 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.900 ns + " "Info: + Micro hold delay of destination is 0.900 ns" {  } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 64 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.700 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns dividend\[3\] 1 PIN PIN_70 1 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_70; Fanout = 1; PIN Node = 'dividend\[3\]'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "" { dividend[3] } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(1.300 ns) 7.700 ns remainder\[4\]~reg0 2 REG LC5_J40 5 " "Info: 2: + IC(3.300 ns) + CELL(1.300 ns) = 7.700 ns; Loc. = LC5_J40; Fanout = 5; REG Node = 'remainder\[4\]~reg0'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "4.600 ns" { dividend[3] remainder[4]~reg0 } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 64 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.400 ns 57.14 % " "Info: Total cell delay = 4.400 ns ( 57.14 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns 42.86 % " "Info: Total interconnect delay = 3.300 ns ( 42.86 % )" {  } {  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "7.700 ns" { dividend[3] remainder[4]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.700 ns" { dividend[3] dividend[3]~out remainder[4]~reg0 } { 0.000ns 0.000ns 3.300ns } { 0.000ns 3.100ns 1.300ns } } }  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "1.900 ns" { clock remainder[4]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out remainder[4]~reg0 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "7.700 ns" { dividend[3] remainder[4]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.700 ns" { dividend[3] dividend[3]~out remainder[4]~reg0 } { 0.000ns 0.000ns 3.300ns } { 0.000ns 3.100ns 1.300ns } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clock remainder\[8\] remainder\[8\]~reg0 12.400 ns register " "Info: Minimum tco from clock \"clock\" to destination pin \"remainder\[8\]\" through register \"remainder\[8\]~reg0\" is 12.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 1.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clock 1 CLK PIN_79 18 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 18; CLK Node = 'clock'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "" { clock } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns remainder\[8\]~reg0 2 REG LC2_J38 3 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC2_J38; Fanout = 3; REG Node = 'remainder\[8\]~reg0'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "1.400 ns" { clock remainder[8]~reg0 } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 64 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns 26.32 % " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 73.68 % " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "1.900 ns" { clock remainder[8]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out remainder[8]~reg0 } { 0.0ns 0.0ns 1.4ns } { 0.0ns 0.5ns 0.0ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 64 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.400 ns + Shortest register pin " "Info: + Shortest register to pin delay is 9.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns remainder\[8\]~reg0 1 REG LC2_J38 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_J38; Fanout = 3; REG Node = 'remainder\[8\]~reg0'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "" { remainder[8]~reg0 } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 64 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(8.600 ns) 9.400 ns remainder\[8\] 2 PIN PIN_39 0 " "Info: 2: + IC(0.800 ns) + CELL(8.600 ns) = 9.400 ns; Loc. = PIN_39; Fanout = 0; PIN Node = 'remainder\[8\]'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "9.400 ns" { remainder[8]~reg0 remainder[8] } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.600 ns 91.49 % " "Info: Total cell delay = 8.600 ns ( 91.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.800 ns 8.51 % " "Info: Total interconnect delay = 0.800 ns ( 8.51 % )" {  } {  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "9.400 ns" { remainder[8]~reg0 remainder[8] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.400 ns" { remainder[8]~reg0 remainder[8] } { 0.0ns 0.8ns } { 0.0ns 8.6ns } } }  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "1.900 ns" { clock remainder[8]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out remainder[8]~reg0 } { 0.0ns 0.0ns 1.4ns } { 0.0ns 0.5ns 0.0ns } } } { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "9.400 ns" { remainder[8]~reg0 remainder[8] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.400 ns" { remainder[8]~reg0 remainder[8] } { 0.0ns 0.8ns } { 0.0ns 8.6ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 23 16:26:05 2005 " "Info: Processing ended: Tue Aug 23 16:26:05 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}
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