divider.map.qmsg

这个是用vhdl语言编写的除法器,仅仅供大家参考.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 23 16:25:42 2005 " "Info: Processing started: Tue Aug 23 16:25:42 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off divider -c divider " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off divider -c divider" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "divider.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file divider.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 divider-structural " "Info: Found design unit 1: divider-structural" {  } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 18 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 divider " "Info: Found entity 1: divider" {  } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "divider " "Info: Elaborating entity \"divider\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "remainder divider.vhd(123) " "Warning: VHDL Process Statement warning at divider.vhd(123): signal \"remainder\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 123 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "remainder divider.vhd(138) " "Warning: VHDL Process Statement warning at divider.vhd(138): signal \"remainder\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 138 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "remainder divider.vhd(139) " "Warning: VHDL Process Statement warning at divider.vhd(139): signal \"remainder\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 139 0 0 } }  } 0}
{ "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_HDR" "" "Info: One or more bidirs are fed by always enabled tri-state buffers" { { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "remainder\[0\] " "Info: Fanout of permanently enabled tri-state buffer feeding bidir \"remainder\[0\]\" is moved to its source" {  } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 13 -1 0 } }  } 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "finish " "Info: Fanout of permanently enabled tri-state buffer feeding bidir \"finish\" is moved to its source" {  } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "remainder\[1\] " "Info: Fanout of permanently enabled tri-state buffer feeding bidir \"remainder\[1\]\" is moved to its source" {  } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 13 -1 0 } }  } 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "remainder\[2\] " "Info: Fanout of permanently enabled tri-state buffer feeding bidir \"remainder\[2\]\" is moved to its source" {  } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 13 -1 0 } }  } 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "remainder\[3\] " "Info: Fanout of permanently enabled tri-state buffer feeding bidir \"remainder\[3\]\" is moved to its source" {  } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 13 -1 0 } }  } 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "remainder\[5\] " "Info: Fanout of permanently enabled tri-state buffer feeding bidir \"remainder\[5\]\" is moved to its source" {  } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 13 -1 0 } }  } 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "remainder\[6\] " "Info: Fanout of permanently enabled tri-state buffer feeding bidir \"remainder\[6\]\" is moved to its source" {  } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 13 -1 0 } }  } 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "remainder\[7\] " "Info: Fanout of permanently enabled tri-state buffer feeding bidir \"remainder\[7\]\" is moved to its source" {  } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 13 -1 0 } }  } 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "remainder\[4\] " "Info: Fanout of permanently enabled tri-state buffer feeding bidir \"remainder\[4\]\" is moved to its source" {  } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 13 -1 0 } }  } 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "remainder\[8\] " "Info: Fanout of permanently enabled tri-state buffer feeding bidir \"remainder\[8\]\" is moved to its source" {  } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 13 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_ENABLED_OE" "" "Warning: TRI or OPNDRN buffers permanently enabled" { { "Warning" "WOPT_MLS_NODE_NAME" "remainder\[0\]~45 " "Warning: Node \"remainder\[0\]~45\"" {  } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 13 -1 0 } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "remainder\[1\]~46 " "Warning: Node \"remainder\[1\]~46\"" {  } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 13 -1 0 } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "remainder\[2\]~47 " "Warning: Node \"remainder\[2\]~47\"" {  } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 13 -1 0 } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "remainder\[3\]~48 " "Warning: Node \"remainder\[3\]~48\"" {  } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 13 -1 0 } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "remainder\[4\]~49 " "Warning: Node \"remainder\[4\]~49\"" {  } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 13 -1 0 } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "remainder\[5\]~50 " "Warning: Node \"remainder\[5\]~50\"" {  } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 13 -1 0 } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "remainder\[6\]~51 " "Warning: Node \"remainder\[6\]~51\"" {  } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 13 -1 0 } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "remainder\[7\]~52 " "Warning: Node \"remainder\[7\]~52\"" {  } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 13 -1 0 } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "remainder\[8\]~53 " "Warning: Node \"remainder\[8\]~53\"" {  } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 13 -1 0 } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "finish~1 " "Warning: Node \"finish~1\"" {  } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 14 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "remainder_r\[3\] GND " "Warning: Pin \"remainder_r\[3\]\" stuck at GND" {  } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 12 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "73 " "Info: Implemented 73 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "9 " "Info: Implemented 9 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_BIDIRS" "10 " "Info: Implemented 10 bidirectional pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "46 " "Info: Implemented 46 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 16 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 23 16:25:45 2005 " "Info: Processing ended: Tue Aug 23 16:25:45 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}