divider.tan.rpt

这个是用vhdl语言编写的除法器,仅仅供大家参考.

; Minimum Slack ; Required Min tco ; Actual Min tco ; From              ; To             ; From Clock ;
+---------------+------------------+----------------+-------------------+----------------+------------+
; N/A           ; None             ; 12.400 ns      ; remainder[8]~reg0 ; remainder[8]   ; clock      ;
; N/A           ; None             ; 12.800 ns      ; remainder[4]~reg0 ; remainder[4]   ; clock      ;
; N/A           ; None             ; 13.400 ns      ; finish~reg0       ; finish         ; clock      ;
; N/A           ; None             ; 14.600 ns      ; remainder[2]~reg0 ; remainder[2]   ; clock      ;
; N/A           ; None             ; 14.600 ns      ; remainder[3]~reg0 ; remainder[3]   ; clock      ;
; N/A           ; None             ; 14.700 ns      ; remainder[1]~reg0 ; remainder[1]   ; clock      ;
; N/A           ; None             ; 14.800 ns      ; remainder[0]~reg0 ; remainder[0]   ; clock      ;
; N/A           ; None             ; 14.800 ns      ; remainder[5]~reg0 ; remainder[5]   ; clock      ;
; N/A           ; None             ; 14.800 ns      ; remainder[6]~reg0 ; remainder[6]   ; clock      ;
; N/A           ; None             ; 14.800 ns      ; remainder[7]~reg0 ; remainder[7]   ; clock      ;
; N/A           ; None             ; 16.500 ns      ; remainder[5]~reg0 ; remainder_r[0] ; clock      ;
; N/A           ; None             ; 17.400 ns      ; remainder[7]~reg0 ; remainder_r[2] ; clock      ;
; N/A           ; None             ; 17.600 ns      ; finish~reg0       ; quotient[0]    ; clock      ;
; N/A           ; None             ; 17.800 ns      ; finish~reg0       ; quotient[2]    ; clock      ;
; N/A           ; None             ; 18.000 ns      ; remainder[6]~reg0 ; remainder_r[1] ; clock      ;
; N/A           ; None             ; 18.100 ns      ; remainder[3]~reg0 ; quotient[3]    ; clock      ;
; N/A           ; None             ; 18.200 ns      ; remainder[1]~reg0 ; quotient[1]    ; clock      ;
; N/A           ; None             ; 18.200 ns      ; remainder[2]~reg0 ; quotient[2]    ; clock      ;
; N/A           ; None             ; 18.300 ns      ; finish~reg0       ; quotient[3]    ; clock      ;
; N/A           ; None             ; 18.300 ns      ; finish~reg0       ; remainder_r[0] ; clock      ;
; N/A           ; None             ; 18.300 ns      ; finish~reg0       ; remainder_r[1] ; clock      ;
; N/A           ; None             ; 18.300 ns      ; finish~reg0       ; remainder_r[2] ; clock      ;
; N/A           ; None             ; 18.400 ns      ; remainder[0]~reg0 ; quotient[0]    ; clock      ;
; N/A           ; None             ; 18.400 ns      ; finish~reg0       ; quotient[1]    ; clock      ;
+---------------+------------------+----------------+-------------------+----------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Tue Aug 23 16:26:04 2005
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off divider -c divider
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" has Internal fmax of 74.63 MHz between source register "remainder[7]~reg0" and destination register "remainder[6]~reg0" (period= 13.4 ns)
    Info: + Longest register to register delay is 11.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_J41; Fanout = 9; REG Node = 'remainder[7]~reg0'
        Info: 2: + IC(1.100 ns) + CELL(2.000 ns) = 3.100 ns; Loc. = LC3_J40; Fanout = 1; COMB Node = 'add_op~30'
        Info: 3: + IC(0.200 ns) + CELL(1.700 ns) = 5.000 ns; Loc. = LC1_J40; Fanout = 2; COMB Node = 'carries[0]~359'
        Info: 4: + IC(1.100 ns) + CELL(1.900 ns) = 8.000 ns; Loc. = LC4_J41; Fanout = 2; COMB Node = 'carries[1]~360'
        Info: 5: + IC(0.200 ns) + CELL(2.200 ns) = 10.400 ns; Loc. = LC8_J41; Fanout = 1; COMB Node = 'remainder~2126'
        Info: 6: + IC(0.200 ns) + CELL(1.000 ns) = 11.600 ns; Loc. = LC5_J41; Fanout = 6; REG Node = 'remainder[6]~reg0'
        Info: Total cell delay = 8.800 ns ( 75.86 % )
        Info: Total interconnect delay = 2.800 ns ( 24.14 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clock" to destination register is 1.900 ns
            Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 18; CLK Node = 'clock'
            Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC5_J41; Fanout = 6; REG Node = 'remainder[6]~reg0'
            Info: Total cell delay = 0.500 ns ( 26.32 % )
            Info: Total interconnect delay = 1.400 ns ( 73.68 % )
        Info: - Longest clock path from clock "clock" to source register is 1.900 ns
            Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 18; CLK Node = 'clock'
            Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC1_J41; Fanout = 9; REG Node = 'remainder[7]~reg0'
            Info: Total cell delay = 0.500 ns ( 26.32 % )
            Info: Total interconnect delay = 1.400 ns ( 73.68 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Micro setup delay of destination is 0.700 ns
Info: tsu for register "remainder[3]~reg0" (data pin = "dividend[2]", clock pin = "clock") is 7.100 ns
    Info: + Longest pin to register delay is 8.300 ns
        Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_69; Fanout = 1; PIN Node = 'dividend[2]'
        Info: 2: + IC(3.900 ns) + CELL(1.300 ns) = 8.300 ns; Loc. = LC1_J39; Fanout = 4; REG Node = 'remainder[3]~reg0'
        Info: Total cell delay = 4.400 ns ( 53.01 % )
        Info: Total interconnect delay = 3.900 ns ( 46.99 % )
    Info: + Micro setup delay of destination is 0.700 ns
    Info: - Shortest clock path from clock "clock" to destination register is 1.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 18; CLK Node = 'clock'
        Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC1_J39; Fanout = 4; REG Node = 'remainder[3]~reg0'
        Info: Total cell delay = 0.500 ns ( 26.32 % )
        Info: Total interconnect delay = 1.400 ns ( 73.68 % )
Info: tco from clock "clock" to destination pin "quotient[1]" through register "finish~reg0" is 18.400 ns
    Info: + Longest clock path from clock "clock" to source register is 1.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 18; CLK Node = 'clock'
        Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC4_J38; Fanout = 8; REG Node = 'finish~reg0'
        Info: Total cell delay = 0.500 ns ( 26.32 % )
        Info: Total interconnect delay = 1.400 ns ( 73.68 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Longest register to pin delay is 15.400 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_J38; Fanout = 8; REG Node = 'finish~reg0'
        Info: 2: + IC(1.800 ns) + CELL(1.900 ns) = 3.700 ns; Loc. = LC2_J43; Fanout = 1; COMB Node = 'quotient~42'
        Info: 3: + IC(3.100 ns) + CELL(8.600 ns) = 15.400 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'quotient[1]'
        Info: Total cell delay = 10.500 ns ( 68.18 % )
        Info: Total interconnect delay = 4.900 ns ( 31.82 % )
Info: th for register "remainder[4]~reg0" (data pin = "dividend[3]", clock pin = "clock") is -4.900 ns
    Info: + Longest clock path from clock "clock" to destination register is 1.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 18; CLK Node = 'clock'
        Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC5_J40; Fanout = 5; REG Node = 'remainder[4]~reg0'
        Info: Total cell delay = 0.500 ns ( 26.32 % )
        Info: Total interconnect delay = 1.400 ns ( 73.68 % )
    Info: + Micro hold delay of destination is 0.900 ns
    Info: - Shortest pin to register delay is 7.700 ns
        Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_70; Fanout = 1; PIN Node = 'dividend[3]'
        Info: 2: + IC(3.300 ns) + CELL(1.300 ns) = 7.700 ns; Loc. = LC5_J40; Fanout = 5; REG Node = 'remainder[4]~reg0'
        Info: Total cell delay = 4.400 ns ( 57.14 % )
        Info: Total interconnect delay = 3.300 ns ( 42.86 % )
Info: Minimum tco from clock "clock" to destination pin "remainder[8]" through register "remainder[8]~reg0" is 12.400 ns
    Info: + Shortest clock path from clock "clock" to source register is 1.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 18; CLK Node = 'clock'
        Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC2_J38; Fanout = 3; REG Node = 'remainder[8]~reg0'
        Info: Total cell delay = 0.500 ns ( 26.32 % )
        Info: Total interconnect delay = 1.400 ns ( 73.68 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Shortest register to pin delay is 9.400 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_J38; Fanout = 3; REG Node = 'remainder[8]~reg0'
        Info: 2: + IC(0.800 ns) + CELL(8.600 ns) = 9.400 ns; Loc. = PIN_39; Fanout = 0; PIN Node = 'remainder[8]'
        Info: Total cell delay = 8.600 ns ( 91.49 % )
        Info: Total interconnect delay = 0.800 ns ( 8.51 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Aug 23 16:26:05 2005
    Info: Elapsed time: 00:00:02