89_full_adder.map.qmsg

这个是带先行进位的加法器的vhdl代码,比较复杂,仅仅供大家参考.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Feb 19 23:35:34 2006 " "Info: Processing started: Sun Feb 19 23:35:34 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off 89_Full_adder -c 89_Full_adder " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off 89_Full_adder -c 89_Full_adder" {  } {  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_COMPILED_IN_LIBRARY" "BIT_FUNCTIONS work 89_Full_adder.vhd(9) " "Error: VHDL Use Clause error at 89_Full_adder.vhd(9): design library \"work\" does not contain primary unit \"BIT_FUNCTIONS\"" {  } { { "89_Full_adder.vhd" "" { Text "F:/学习资料/vhdl实验/100例/200441123245276683/100vhdl例子/89_full_adder/89_Full_adder.vhd" 9 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_UNIT_INGONRED_ERR" "FULL_ADDER 89_Full_adder.vhd(11) " "Error: Ignored construct FULL_ADDER at 89_Full_adder.vhd(11) because of previous errors" {  } { { "89_Full_adder.vhd" "" { Text "F:/学习资料/vhdl实验/100例/200441123245276683/100vhdl例子/89_full_adder/89_Full_adder.vhd" 11 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_UNCOMPILED_ENTITY" "FULL_ADDER 89_Full_adder.vhd(21) " "Error: VHDL error at 89_Full_adder.vhd(21): entity \"FULL_ADDER\" is used but not declared" {  } { { "89_Full_adder.vhd" "" { Text "F:/学习资料/vhdl实验/100例/200441123245276683/100vhdl例子/89_full_adder/89_Full_adder.vhd" 21 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "BIT_VECTOR 89_Full_adder.vhd(22) " "Error: VHDL error at 89_Full_adder.vhd(22): object \"BIT_VECTOR\" is used but not declared" {  } { { "89_Full_adder.vhd" "" { Text "F:/学习资料/vhdl实验/100例/200441123245276683/100vhdl例子/89_full_adder/89_Full_adder.vhd" 22 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "BIT 89_Full_adder.vhd(23) " "Error: VHDL error at 89_Full_adder.vhd(23): object \"BIT\" is used but not declared" {  } { { "89_Full_adder.vhd" "" { Text "F:/学习资料/vhdl实验/100例/200441123245276683/100vhdl例子/89_full_adder/89_Full_adder.vhd" 23 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "BIT_VECTOR 89_Full_adder.vhd(24) " "Error: VHDL error at 89_Full_adder.vhd(24): object \"BIT_VECTOR\" is used but not declared" {  } { { "89_Full_adder.vhd" "" { Text "F:/学习资料/vhdl实验/100例/200441123245276683/100vhdl例子/89_full_adder/89_Full_adder.vhd" 24 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "BIT_VECTOR 89_Full_adder.vhd(25) " "Error: VHDL error at 89_Full_adder.vhd(25): object \"BIT_VECTOR\" is used but not declared" {  } { { "89_Full_adder.vhd" "" { Text "F:/学习资料/vhdl实验/100例/200441123245276683/100vhdl例子/89_full_adder/89_Full_adder.vhd" 25 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "BIT_VECTOR 89_Full_adder.vhd(26) " "Error: VHDL error at 89_Full_adder.vhd(26): object \"BIT_VECTOR\" is used but not declared" {  } { { "89_Full_adder.vhd" "" { Text "F:/学习资料/vhdl实验/100例/200441123245276683/100vhdl例子/89_full_adder/89_Full_adder.vhd" 26 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "sA 89_Full_adder.vhd(29) " "Error: VHDL error at 89_Full_adder.vhd(29): object \"sA\" is used but not declared" {  } { { "89_Full_adder.vhd" "" { Text "F:/学习资料/vhdl实验/100例/200441123245276683/100vhdl例子/89_full_adder/89_Full_adder.vhd" 29 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "sB 89_Full_adder.vhd(30) " "Error: VHDL error at 89_Full_adder.vhd(30): object \"sB\" is used but not declared" {  } { { "89_Full_adder.vhd" "" { Text "F:/学习资料/vhdl实验/100例/200441123245276683/100vhdl例子/89_full_adder/89_Full_adder.vhd" 30 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "sCin 89_Full_adder.vhd(31) " "Error: VHDL error at 89_Full_adder.vhd(31): object \"sCin\" is used but not declared" {  } { { "89_Full_adder.vhd" "" { Text "F:/学习资料/vhdl实验/100例/200441123245276683/100vhdl例子/89_full_adder/89_Full_adder.vhd" 31 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "sT 89_Full_adder.vhd(32) " "Error: VHDL error at 89_Full_adder.vhd(32): object \"sT\" is used but not declared" {  } { { "89_Full_adder.vhd" "" { Text "F:/学习资料/vhdl实验/100例/200441123245276683/100vhdl例子/89_full_adder/89_Full_adder.vhd" 32 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "sG 89_Full_adder.vhd(33) " "Error: VHDL error at 89_Full_adder.vhd(33): object \"sG\" is used but not declared" {  } { { "89_Full_adder.vhd" "" { Text "F:/学习资料/vhdl实验/100例/200441123245276683/100vhdl例子/89_full_adder/89_Full_adder.vhd" 33 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "sT 89_Full_adder.vhd(34) " "Error: VHDL error at 89_Full_adder.vhd(34): object \"sT\" is used but not declared" {  } { { "89_Full_adder.vhd" "" { Text "F:/学习资料/vhdl实验/100例/200441123245276683/100vhdl例子/89_full_adder/89_Full_adder.vhd" 34 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "sG 89_Full_adder.vhd(35) " "Error: VHDL error at 89_Full_adder.vhd(35): object \"sG\" is used but not declared" {  } { { "89_Full_adder.vhd" "" { Text "F:/学习资料/vhdl实验/100例/200441123245276683/100vhdl例子/89_full_adder/89_Full_adder.vhd" 35 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "sT 89_Full_adder.vhd(36) " "Error: VHDL error at 89_Full_adder.vhd(36): object \"sT\" is used but not declared" {  } { { "89_Full_adder.vhd" "" { Text "F:/学习资料/vhdl实验/100例/200441123245276683/100vhdl例子/89_full_adder/89_Full_adder.vhd" 36 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "sG 89_Full_adder.vhd(37) " "Error: VHDL error at 89_Full_adder.vhd(37): object \"sG\" is used but not declared" {  } { { "89_Full_adder.vhd" "" { Text "F:/学习资料/vhdl实验/100例/200441123245276683/100vhdl例子/89_full_adder/89_Full_adder.vhd" 37 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "sT 89_Full_adder.vhd(38) " "Error: VHDL error at 89_Full_adder.vhd(38): object \"sT\" is used but not declared" {  } { { "89_Full_adder.vhd" "" { Text "F:/学习资料/vhdl实验/100例/200441123245276683/100vhdl例子/89_full_adder/89_Full_adder.vhd" 38 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "sG 89_Full_adder.vhd(39) " "Error: VHDL error at 89_Full_adder.vhd(39): object \"sG\" is used but not declared" {  } { { "89_Full_adder.vhd" "" { Text "F:/学习资料/vhdl实验/100例/200441123245276683/100vhdl例子/89_full_adder/89_Full_adder.vhd" 39 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "89_Full_adder.vhd 0 0 " "Info: Found 0 design units, including 0 entities, in source file 89_Full_adder.vhd" {  } {  } 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 19 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 19 errors, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Sun Feb 19 23:35:37 2006 " "Error: Processing ended: Sun Feb 19 23:35:37 2006" {  } {  } 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:03 " "Error: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}