89_full_adder.map.rpt

这个是带先行进位的加法器的vhdl代码,比较复杂,仅仅供大家参考.

Analysis & Synthesis report for 89_Full_adder
Sun Feb 19 23:35:37 2006
Version 5.0 Build 148 04/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Failed - Sun Feb 19 23:35:37 2006        ;
; Quartus II Version          ; 5.0 Build 148 04/26/2005 SJ Full Version ;
; Revision Name               ; 89_Full_adder                            ;
; Top-level Entity Name       ; 89_Full_adder                            ;
; Family                      ; ACEX1K                                   ;
+-----------------------------+------------------------------------------+


+---------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                               ;
+------------------------------------------------------------+----------------+---------------+
; Option                                                     ; Setting        ; Default Value ;
+------------------------------------------------------------+----------------+---------------+
; Device                                                     ; EP1K100QC208-3 ;               ;
; Top-level entity name                                      ; 89_Full_adder  ; 89_Full_adder ;
; Family name                                                ; ACEX1K         ; Stratix       ;
; Use smart compilation                                      ; Off            ; Off           ;
; Create Debugging Nodes for IP Cores                        ; off            ; off           ;
; Preserve fewer node names                                  ; On             ; On            ;
; Disable OpenCore Plus hardware evaluation                  ; Off            ; Off           ;
; Verilog Version                                            ; Verilog_2001   ; Verilog_2001  ;
; VHDL Version                                               ; VHDL93         ; VHDL93        ;
; State Machine Processing                                   ; Auto           ; Auto          ;
; Extract Verilog State Machines                             ; On             ; On            ;
; Extract VHDL State Machines                                ; On             ; On            ;
; Add Pass-Through Logic to Inferred RAMs                    ; On             ; On            ;
; NOT Gate Push-Back                                         ; On             ; On            ;
; Power-Up Don't Care                                        ; On             ; On            ;
; Remove Redundant Logic Cells                               ; Off            ; Off           ;
; Remove Duplicate Registers                                 ; On             ; On            ;
; Ignore CARRY Buffers                                       ; Off            ; Off           ;
; Ignore CASCADE Buffers                                     ; Off            ; Off           ;
; Ignore GLOBAL Buffers                                      ; Off            ; Off           ;
; Ignore ROW GLOBAL Buffers                                  ; Off            ; Off           ;
; Ignore LCELL Buffers                                       ; Off            ; Off           ;
; Ignore SOFT Buffers                                        ; On             ; On            ;
; Limit AHDL Integers to 32 Bits                             ; Off            ; Off           ;
; Auto Implement in ROM                                      ; Off            ; Off           ;
; Optimization Technique -- FLEX 10K/10KE/10KA/ACEX 1K       ; Area           ; Area          ;
; Carry Chain Length -- FLEX 10K                             ; 32             ; 32            ;
; Cascade Chain Length                                       ; 2              ; 2             ;
; Auto Carry Chains                                          ; On             ; On            ;
; Auto Open-Drain Pins                                       ; On             ; On            ;
; Remove Duplicate Logic                                     ; On             ; On            ;
; Auto ROM Replacement                                       ; On             ; On            ;
; Auto RAM Replacement                                       ; On             ; On            ;
; Auto Clock Enable Replacement                              ; On             ; On            ;
; Auto Resource Sharing                                      ; Off            ; Off           ;
; Allow Any RAM Size For Recognition                         ; Off            ; Off           ;
; Allow Any ROM Size For Recognition                         ; Off            ; Off           ;
; Ignore translate_off and translate_on Synthesis Directives ; Off            ; Off           ;
; Show Parameter Settings Tables in Synthesis Report         ; On             ; On            ;
+------------------------------------------------------------+----------------+---------------+


+-----------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                        ;
+----------------------------------+-----------------+-----------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------+------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sun Feb 19 23:35:34 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off 89_Full_adder -c 89_Full_adder
Error: VHDL Use Clause error at 89_Full_adder.vhd(9): design library "work" does not contain primary unit "BIT_FUNCTIONS"
Error: Ignored construct FULL_ADDER at 89_Full_adder.vhd(11) because of previous errors
Error: VHDL error at 89_Full_adder.vhd(21): entity "FULL_ADDER" is used but not declared
Error: VHDL error at 89_Full_adder.vhd(22): object "BIT_VECTOR" is used but not declared
Error: VHDL error at 89_Full_adder.vhd(23): object "BIT" is used but not declared
Error: VHDL error at 89_Full_adder.vhd(24): object "BIT_VECTOR" is used but not declared
Error: VHDL error at 89_Full_adder.vhd(25): object "BIT_VECTOR" is used but not declared
Error: VHDL error at 89_Full_adder.vhd(26): object "BIT_VECTOR" is used but not declared
Error: VHDL error at 89_Full_adder.vhd(29): object "sA" is used but not declared
Error: VHDL error at 89_Full_adder.vhd(30): object "sB" is used but not declared
Error: VHDL error at 89_Full_adder.vhd(31): object "sCin" is used but not declared
Error: VHDL error at 89_Full_adder.vhd(32): object "sT" is used but not declared
Error: VHDL error at 89_Full_adder.vhd(33): object "sG" is used but not declared
Error: VHDL error at 89_Full_adder.vhd(34): object "sT" is used but not declared
Error: VHDL error at 89_Full_adder.vhd(35): object "sG" is used but not declared
Error: VHDL error at 89_Full_adder.vhd(36): object "sT" is used but not declared
Error: VHDL error at 89_Full_adder.vhd(37): object "sG" is used but not declared
Error: VHDL error at 89_Full_adder.vhd(38): object "sT" is used but not declared
Error: VHDL error at 89_Full_adder.vhd(39): object "sG" is used but not declared
Info: Found 0 design units, including 0 entities, in source file 89_Full_adder.vhd
Error: Quartus II Analysis & Synthesis was unsuccessful. 19 errors, 0 warnings
    Error: Processing ended: Sun Feb 19 23:35:37 2006
    Error: Elapsed time: 00:00:03