89_full_adder.map.talkback.xml

这个是带先行进位的加法器的vhdl代码,比较复杂,仅仅供大家参考.

<!--
This XML file (created on Sun Feb 19 23:35:37 2006) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to license.txt.
-->
<talkback>
<ver>5.0</ver>
<schema>quartus_version_5.0_build_148.xsd</schema><license>
	<nic_id>00046168ea2d</nic_id>
	<cdrive_id>6478c66c</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.0</version>
	<build>Build 148</build>
	<module>quartus_map.exe</module>
	<edition>Full Version (Eval)</edition>
	<compilation_end_time>Sun Feb 19 23:35:37 2006</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>1</proc_count>
		<cpu_freq units="MHz">1799</cpu_freq>
	</cpu>
	<ram units="MB">512</ram>
</machine>
<top_file>F:/学习资料/vhdl实验/100例/200441123245276683/100vhdl例子/89_full_adder/89_Full_adder</top_file>
<mep_data>
	<command_line>quartus_map --read_settings_files=on --write_settings_files=off 89_Full_adder -c 89_Full_adder</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<analysis___synthesis_settings>
	<row>
		<option>Device</option>
		<setting>EP1K100QC208-3</setting>
	</row>
	<row>
		<option>Top-level entity name</option>
		<setting>89_Full_adder</setting>
		<default_value>89_Full_adder</default_value>
	</row>
	<row>
		<option>Family name</option>
		<setting>ACEX1K</setting>
		<default_value>Stratix</default_value>
	</row>
	<row>
		<option>Use smart compilation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Create Debugging Nodes for IP Cores</option>
		<setting>off</setting>
		<default_value>off</default_value>
	</row>
	<row>
		<option>Preserve fewer node names</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Disable OpenCore Plus hardware evaluation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Verilog Version</option>
		<setting>Verilog_2001</setting>
		<default_value>Verilog_2001</default_value>
	</row>
	<row>
		<option>VHDL Version</option>
		<setting>VHDL93</setting>
		<default_value>VHDL93</default_value>
	</row>
	<row>
		<option>State Machine Processing</option>
		<setting>Auto</setting>
		<default_value>Auto</default_value>
	</row>
	<row>
		<option>Extract Verilog State Machines</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Extract VHDL State Machines</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Add Pass-Through Logic to Inferred RAMs</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>NOT Gate Push-Back</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Power-Up Don&apos;t Care</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Remove Redundant Logic Cells</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Remove Duplicate Registers</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Ignore CARRY Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore CASCADE Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore GLOBAL Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore ROW GLOBAL Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore LCELL Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore SOFT Buffers</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Limit AHDL Integers to 32 Bits</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Auto Implement in ROM</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Optimization Technique -- FLEX 10K/10KE/10KA/ACEX 1K</option>
		<setting>Area</setting>
		<default_value>Area</default_value>
	</row>
	<row>
		<option>Carry Chain Length -- FLEX 10K</option>
		<setting>32</setting>
		<default_value>32</default_value>
	</row>
	<row>
		<option>Cascade Chain Length</option>
		<setting>2</setting>
		<default_value>2</default_value>
	</row>
	<row>
		<option>Auto Carry Chains</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Open-Drain Pins</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Remove Duplicate Logic</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto ROM Replacement</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto RAM Replacement</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Clock Enable Replacement</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Resource Sharing</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Allow Any RAM Size For Recognition</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Allow Any ROM Size For Recognition</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore translate_off and translate_on Synthesis Directives</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Show Parameter Settings Tables in Synthesis Report</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
</analysis___synthesis_settings>
<compilation_summary>
	<flow_status>Flow Failed - Sun Feb 19 23:35:37 2006</flow_status>
	<quartus_ii_version>5.0 Build 148 04/26/2005 SJ Full Version</quartus_ii_version>
	<revision_name>89_Full_adder</revision_name>
	<top_level_entity_name>89_Full_adder</top_level_entity_name>
	<family>ACEX1K</family>
	<device>EP1K100QC208-3</device>
	<timing_models>Final</timing_models>
	<met_timing_requirements>N/A</met_timing_requirements>
</compilation_summary>
<compile_id>2D0D98F4</compile_id>
</talkback>