pci_c.tdf

Altera AHDL语言设计的PCI总线Core,很难得的PCI设计资料

	frame_out		= mstr.frame_out		;	-- FRAMEn Output Register
	frame_oe		= mstr.frame_oe			;	-- Frame Output Enable
	irdy_out		= mstr.irdy_out			;	-- IRDYn Output Register
	irdy_oe			= mstr.irdy_oe			;	-- IRDYn Output Enable
	req64_out		= mstr.req64_out		;	-- IRDYn Output Register
	req64_oe		= mstr.req64_oe			;	-- IRDYn Output Enable

	req_out			= mstr.req_out			;	-- PCI Bus Request Output Register

	-- Parity Signals
	mstr_perr_vld	= mstr.perr_vld			;	-- Parity Error was detected
	mstr_perr_oe	= mstr.perr_oe			;	-- PERR Output Enable
	mstr_par_oe		= mstr.par_oe			;	-- PAR Output Enable

	-- Configuration Space Outputs
	perr_rep_set	= mstr.perr_rep_set		;	-- Set Command Register Target Abort Recieved Bit
	targ_abrt_set	= mstr.targ_abrt_set	;	-- Set Command Register Target Abort Recieved Bit
	mstr_abrt_set	= mstr.mstr_abrt_set	;	-- Set Command Regsiter Master Abort Recieved Bit
	
	-- Local Side Outputs
	lm_adr_ack		= mstr.lm_adr_ack		; 	-- Local Master Address Acknowledge
	lm_ackn			= mstr.lm_ackn			;	-- PCI/B Ready/Acknowledge Signal
--	trdyrn			= mstr.trdyrn			;	-- This is a registered version of PCI trdyn signal

	lm_ldata_ackn = mstr.lm_ldata_ackn;
	lm_hdata_ackn = mstr.lm_hdata_ackn;
	lm_dxfrn	    = mstr.lm_dxfrn;

	lm_tsr[9..0]	= mstr.lm_tsr[9..0]		;	-- Master Transaction Status Registers
	mstr_actv		= mstr.mstr_actv		;   -- Master is Active.  Has PCI Bus
	mstr_dac_decode	= mstr.dac_decode_out		; 	-- Dual Address decode

-- *************************************************************************************************

--	junk = trg_adr_phase_out or mstr_actv;

	perr			= NOT perrn;		-- Active high perr Input

	perr_oe_R.clk	= clk;			-- PERRn Output Enable Register
	perr_oe_R.clrn	= rstn;
	perr_oe_R		= trg_perr_oe OR mstr_perr_oe; 
	
	perrn			= TRI(NOT perr_out, perr_oe_R);			-- PERRn Output

	-- SERRn Signal

	serrn			= OPNDRN(NOT serr_out);	-- SERRn Output

	-- par Signals

	par_or.clk		= clk ;			-- par output regsister
	par_or.clrn		= rstn;	
	par_or			= par_gen_out;	

	par_or64.clk		= clk ;			-- par output regsister
	par_or64.clrn		= rstn;	
--	par_or64.ena		= not trg_cfg_cyc_out;
	par_or64			= par_gen_out64;	
	
	par_oeR.clk		= clk;
	par_oeR.clrn 	= rstn;
	par_oeR			= trg_par_oe OR mstr_par_oe;
	par_oe			= par_oeR;

	par				= TRI(par_or, par_oe);		-- par Output
	par64			= TRI(par_or64, par_oe);	-- par64 Output
	

	-- AD OUTPUT Bus Signals
	
	l_dato[31..0]	= low_ad_IR_data[31..0];	-- Local Data Output
	
	-- Local Data Output
	l_dato[63..32]	= 	(high_ad_IR_data[31..0]	and 	local_dat_sel) 
					OR	(low_ad_IR_data[31..0] 	and not local_dat_sel);	

	
	local_dat_sel	= 	(not lt_hdata_ackn and not lt_ldata_ackn and lt_sel_w) 
					OR	(not lm_hdata_ackn and not lm_ldata_ackn and not lt_sel_w and mstr_64_trans_out);
					

--jot	l_ldat_ackn 	= 	(lt_ldata_ackn and lt_sel_w) 
--jot					OR	(lm_ldata_ackn and not lt_sel_w);

--jot	l_hdat_ackn 	= 	(lt_hdata_ackn and lt_sel_w) 
--jot					OR	(lm_hdata_ackn and not lt_sel_w);

	l_ldat_ack 	= 	(not lt_ldata_ackn and lt_sel_w) 
					OR	(not lm_ldata_ackn and not lt_sel_w);

	l_hdat_ack 	= 	(not lt_hdata_ackn and lt_sel_w) 
					OR	(not lm_hdata_ackn and not lt_sel_w);

	 
	l_ldat_ackn	= not l_ldat_ack;
	l_hdat_ackn	= not l_hdat_ack;

	


	l_beno[3..0]	= low_cben_IR_data[3..0];	-- Local Data Output
	
	l_beno[7..4]	= 	(high_cben_IR_data[3..0] and local_dat_sel) 
					OR	(low_cben_IR_data[3..0] and not local_dat_sel);	-- Local Data Output

	ad_ce_nc		= 	lcell (trg_ADOR_ena 
					OR	mstr_ADOR_ena);
					
--	ad_ce			= (trdy and irdy) OR ad_ce_nc;

----------LOW Data Output----------------

-- OPTIMIZATION	low_trg_dat_out[31..0] 		= 	(trg_low_data_out[31..0] and not trg_cfg_cyc_out and not trg_hr_dat_sel)--low_trg_dat_out_lc1[]
-- OPTIMIZATION								 	OR 	(low_data_out_HR[31..0] and not trg_cfg_cyc_out and trg_hr_dat_sel); -- 4 INPUTS
--								 	OR	(trg_cfg_dat_out[31..0] and trg_cfg_cyc_out);
	
--6/8	low_trg_dat_out[31..0] 		= 	(trg_low_data_out[31..0] and not trg_hr_dat_sel)--low_trg_dat_out_lc1[]
--6/8								 	OR 	(low_data_out_HR[31..0] and trg_hr_dat_sel); -- 4 INPUTS

--6/8	low_trg_dat_out[31..0] 		= 	(trg_low_data_out[31..0] and not mstr_trg_hr_dat_sel)--low_trg_dat_out_lc1[] -- trg_low_data_out = l_adi[31..0]
--6/8								 	OR 	(low_data_out_HR[31..0] and mstr_trg_hr_dat_sel); -- 4 INPUTS


--OPTIMIZATION	low_trg_dat_out_lc1[]		=	(trg_low_data_out[31..0] and not trg_cfg_cyc_out and not trg_hr_dat_sel)
--OPTIMIZATION												OR 	(low_data_out_HR[31..0] and not trg_cfg_cyc_out and trg_hr_dat_sel);

--6/8	low_mstr_dat_out[31..0] 	= 	(mstr_low_data_out[31..0] and not mstr_hr_dat_sel)
--6/8								OR	(low_data_out_HR[31..0] and mstr_hr_dat_sel);

--6/8	low_mstr_dat_out[31..0] 	= 	(mstr_low_data_out[31..0] and not mstr_trg_hr_dat_sel) -- mstr_low_data_out = l_adi[31..0]
--6/8								OR	(low_data_out_HR[31..0] and mstr_trg_hr_dat_sel);


	low_mstr_cbe_out[]			= 	(mstr_low_cbe_out[3..0] and not mstr_hr_cbe_sel and not mstr_hi_low_sel)
								OR	(low_cbe_out_HR[3..0] and mstr_hr_cbe_sel and not mstr_hi_low_sel)
								or  (high_cbe_out_HR[3..0] and mstr_hi_low_sel);

	low_data_out_HR[]			= 	(trg_low_data_out[] and trg_ad_sel )
								OR	(mstr_low_data_out[] and mstr_ad_sel);
								
	low_data_out_HR[].clk		= clk;
	low_data_out_HR[].clrn		= rstn;
	low_data_out_HR[].ena		= 	low_data_out_hr_ena_d;-- Holding Register Enable Signal
	low_data_out_hr_ena_d		=	LCELL(trg_dati_HR_ena # mstr_dati_HR_ena);
	low_cbe_out_HR[]			= mstr_low_cbe_out[];

	low_cbe_out_HR[].clk		= clk;
	low_cbe_out_HR[].clrn		= rstn;
	low_cbe_out_HR[].ena		= mstr_cbe_HR_ena;

--6/8	low_ad_out_lc1[]		= 	((low_trg_dat_out[31..0] OR	(trg_cfg_dat_out[31..0] and trg_cfg_cyc_out)) and trg_low_ad_out_sel)
--6/8								OR (low_mstr_dat_out[31..0] and mstr_low_ad_out_sel);

	low_ad_out_lc1[]		= 	(trg_cfg_dat_out[31..0] and trg_cfg_cyc_out and trg_low_ad_out_sel) OR low_ad_out_lc2[];



--OPTIMIZATION	low_ad_out[]			= low_ad_out_lc1[]
--OPTIMIZATION							OR (high_ad_or[63..32] and high_low_ad_out_sel);
	
--6/8	low_ad_out[]			= low_ad_out_lc1[]
--6/8							OR (high_ad_or[63..32] and not(trg_low_ad_out_sel or mstr_low_ad_out_sel));-- high_low_ad_out_sel);

	low_ad_out_lc2[] 	= (low_data_out_HR[] and mstr_trg_hr_dat_sel and mstr_trg_low_ad_out_sel)
							OR (high_ad_or[63..32] and not(mstr_trg_low_ad_out_sel));-- and not l_adro2);
--							OR (trg_high_data_out and not(mstr_trg_low_ad_out_sel) and l_adro2);-- high_low_ad_out_sel);
							


	mstr_trg_low		= LCELL(not mstr_trg_hr_dat_sel and mstr_trg_low_ad_out_sel and not trg_cfg_cyc_out);

	low_ad_out[]		= low_ad_out_lc1[]
							OR ((trg_low_data_out[] or mstr_low_data_out[]) and mstr_trg_low);
								--trg_low_data_out = mstr_low_data_out = l_adi[31..0]
							
	mstr_trg_hr_dat_sel		= mstr_hr_dat_sel or trg_hr_dat_sel;					
--	mstr_trg_ad_sel			= ((mstr_ad_sel or trg_ad_sel) and not trg_cfg_cyc_out);
--	mstr_trg_hi_low_sel		= mstr_hi_low_sel or hi_low_sel;

	trg_low_ad_out_sel		= LCELL(trg_ad_sel and not hi_low_sel );
--6/8	mstr_low_ad_out_sel		= LCELL(mstr_ad_sel and not mstr_hi_low_sel);

	mstr_trg_low_ad_out_sel		= LCELL((mstr_ad_sel or trg_ad_sel) and not (mstr_hi_low_sel or hi_low_sel));



--OPTIMIZATION	high_low_ad_out_sel		= (hi_low_sel or mstr_hi_low_sel);



	IF (TARGET_DEVICE == "EPF10K100EFC484") GENERATE
		
		ad_ce[9..0]	= (trdy and irdy) or ad_ce_nc;
		
		low_ad_or[1..0].ena	= ad_ce0;
		low_ad_or[4].ena	= ad_ce0;
		low_ad_or[3..2].ena	= ad_ce1;
		low_ad_or[11..10].ena	= ad_ce1;
		low_ad_or[7..5].ena	= ad_ce2;
		low_ad_or[9..8].ena	= ad_ce3;
		low_ad_or[12].ena	= ad_ce3;
		low_ad_or[13].ena	= ad_ce4;
		low_ad_or[17].ena	= ad_ce4;
		low_ad_or[16..15].ena	= ad_ce5;
		low_ad_or[20].ena	= ad_ce5;
		low_ad_or[14].ena	= ad_ce6;
		low_ad_or[18].ena	= ad_ce6;
		low_ad_or[21].ena	= ad_ce6;
		low_ad_or[23].ena	= ad_ce6;
		low_ad_or[19].ena	= ad_ce7;
		low_ad_or[24].ena	= ad_ce7;
		low_ad_or[29].ena	= ad_ce7;
		low_ad_or[30].ena	= ad_ce7;
		low_ad_or[22].ena	= ad_ce8;
		low_ad_or[26].ena	= ad_ce8;
		low_ad_or[25].ena	= ad_ce9;
		low_ad_or[28..27].ena	= ad_ce9;
		low_ad_or[31].ena	= ad_ce9;
	ELSE GENERATE
		IF (TARGET_DEVICE == "EPF10K50EFC484") GENERATE
			
			ad_ce[13..0]	= (trdy and irdy) or ad_ce_nc;
		
			low_ad_or[0].ena	= ad_ce0;
			low_ad_or[30].ena = ad_ce0;
			low_ad_or[7].ena = ad_ce0;
			low_ad_or[23].ena = ad_ce0;
			low_ad_or[15].ena = ad_ce0;
			low_ad_or[1].ena	= ad_ce1;
			low_ad_or[8].ena = ad_ce1;
			low_ad_or[29].ena = ad_ce1;
			low_ad_or[24].ena = ad_ce1;
			low_ad_or[16].ena = ad_ce1;
			low_ad_or[9].ena	= ad_ce2;
			low_ad_or[31].ena = ad_ce2;
			low_ad_or[25].ena = ad_ce2;
			low_ad_or[17].ena = ad_ce2;
			low_ad_or[26].ena = ad_ce3;
			low_ad_or[2].ena = ad_ce3;
			low_ad_or[18].ena = ad_ce3;
			low_ad_or[10].ena	= ad_ce3;
			low_ad_or[27].ena	= ad_ce4;
			low_ad_or[19].ena	= ad_ce4;
			low_ad_or[20].ena	= ad_ce4;	
			low_ad_or[3].ena	= ad_ce5;
			low_ad_or[14].ena	= ad_ce5;	
			low_ad_or[4].ena	= ad_ce6;
			low_ad_or[5].ena	= ad_ce7;
			low_ad_or[6].ena	= ad_ce8;
			low_ad_or[11].ena	= ad_ce9;	
			low_ad_or[12].ena	= ad_ce10;	
			low_ad_or[22].ena	= ad_ce10;		
			low_ad_or[13].ena	= ad_ce11;
			low_ad_or[21].ena	= ad_ce12;
			low_ad_or[28].ena	= ad_ce13;						
		ELSE GENERATE
			IF (TARGET_DEVICE == "EPF10K200EFC672") GENERATE

				ad_ce[9..0]	= (trdy and irdy) or ad_ce_nc;
		
				low_ad_or[1..0].ena	= ad_ce0;
				low_ad_or[5..2].ena = ad_ce1;
				low_ad_or[8..6].ena = ad_ce2;
				low_ad_or[11].ena = ad_ce2;
				low_ad_or[10..9].ena = ad_ce3;
				low_ad_or[13].ena = ad_ce3;
				low_ad_or[15].ena = ad_ce3;
				low_ad_or[12].ena = ad_ce4;
				low_ad_or[14].ena = ad_ce4;
				low_ad_or[17].ena = ad_ce4;
				low_ad_or[19].ena = ad_ce4;
				low_ad_or[16].ena = ad_ce5;
				low_ad_or[18].ena = ad_ce5;
				low_ad_or[20].ena = ad_ce5;
				low_ad_or[21].ena = ad_ce6;
				low_ad_or[23].ena = ad_ce6;
				low_ad_or[26..25].ena = ad_ce6;
				low_ad_or[22].ena = ad_ce7;
				low_ad_or[28].ena	= ad_ce7;
				low_ad_or[30].ena	= ad_ce7;
				low_ad_or[27].ena	= ad_ce8;
				low_ad_or[24].ena	= ad_ce8;
				low_ad_or[31].ena	= ad_ce9;
				low_ad_or[29].ena	= ad_ce9;
			ELSE GENERATE
				IF (TARGET_DEVICE == "EPF10K130EFC484") GENERATE

					ad_ce[9..0]	= (trdy and irdy) or ad_ce_nc;
		
					low_ad_or[0].ena	= ad_ce0;
					low_ad_or[4].ena	= ad_ce0;
					low_ad_or[7].ena	= ad_ce0;
					low_ad_or[9].ena	= ad_ce0;
					low_ad_or[2..1].ena = ad_ce1;
					low_ad_or[3].ena = ad_ce2;
					low_ad_or[6..5].ena = ad_ce2;
					low_ad_or[8].ena = ad_ce2;
					low_ad_or[10].ena = ad_ce3;
					low_ad_or[15..14].ena = ad_ce3;
					low_ad_or[13..11].ena = ad_ce4;
					low_ad_or[20].ena = ad_ce4;
					low_ad_or[19..16].ena = ad_ce5;
					low_ad_or[24..21].ena = ad_ce6;
					low_ad_or[26..25].ena = ad_ce7;
					low_ad_or[28].ena	= ad_ce7;
					low_ad_or[27].ena	= ad_ce8;
					low_ad_or[29].ena	= ad_ce8;
					low_ad_or[31..30].ena	= ad_ce9;
				ELSE GENERATE
					IF (TARGET_DEVICE == "NEW") GENERATE

						ad_ce[31..0]		= (trdy and irdy) or ad_ce_nc;		
						low_ad_or[31..0].ena	= ad_ce[31..0];
					ELSE GENERATE

						ad_ce[31..0]		= (trdy and irdy) or ad_ce_nc;		
						low_ad_or[31..0].ena	= ad_ce[31..0];
			
					END GENERATE;
				END GENERATE;
			END GENERATE;
		END GENERATE;
	END GENERATE;



	low_ad_OR[].clk		= clk;			-- AD Output Register
	low_ad_OR[].clrn	= rstn;
--	low_ad_OR[].ena		= ad_ce;
	low_ad_OR[]			= low_ad_out[];

	low_cben_or[].clk	= clk;
	low_cben_or[].clrn	= rstn;
	low_cben_or[].ena	= mstr_cbe_ce;
	low_cben_or[]		= low_mstr_cbe_out[];

----------HIGH Data Output----------------

--OPTIMIZATION	high_trg_dat_out[] 	= (trg_h