vga_sram.v

mining source code written in Verilog

module vga_sram(//input
            clk,
            read,
            radd,
            datain,
            //output
            rscs,
            radc,
            ra,//address
            rd,//data
            rbw,
            rwe,//write
            roe//read 
            );
input clk,read;
input [15:0]radd;
input [31:0]datain;
inout [31:0]rd;

output [15:0]ra;
output [3:0]rbw;
output rscs,radc,rwe,roe;

reg [3:0]rbw;
reg rscs,radc,rwe,roe;

assign ra=radd;
assign rd=rwe?32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz:datain;

always@(posedge clk)
begin  
    //write
   if(read==0)
     begin
     rscs=0;
     radc=0;rwe=0;roe=1;   
     rbw=4'b0000;
     end
   //1x
   if(read==1)
     begin
     rscs=0;
     radc=0;rwe=1;roe=0;
     rbw=4'b1111;
     end
 end
endmodule