keyinmode.v

mining source code written in Verilog

module keyinmode(clk,VGAmodeON,VGAstate,KImode,eokeyin,KIrow,KIcolumn,Lclc,Rclc,X,Y,VGAACK,
                 VGArow,VGAcolumn,OProw,OPcolumn,KIminenum);
input clk;
input VGAmodeON;
output [3:0]VGAstate;
reg [3:0]VGAstate;
input KImode;
reg [1:0]modenum;
output eokeyin;
reg eokeyin;
output [3:0]KIrow,KIcolumn;
reg [3:0]KIrow,KIcolumn;
input Lclc;
input Rclc;
input [3:0]Y,X;
output VGAACK;
reg VGAACK;
input [3:0]VGArow,VGAcolumn;
output [3:0]OProw,OPcolumn;
reg [3:0]OProw,OPcolumn;
output [7:0]KIminenum;
reg [7:0]KIminenum;
reg [7:0]Cbuffer,Rbuffer,buffer,buffer1,buffer2,buffer3,buffer4;
reg start;
always@(posedge clk)
begin
VGAACK=0;
if(KImode==0) eokeyin=0;
if(KImode==1) begin

if(modenum==0)begin
 KIrow=1;KIcolumn=9; start=0;
 if(VGAmodeON==1) begin
  VGAACK=1;
  if(VGArow==1&(VGAcolumn==5|VGAcolumn==6|VGAcolumn==7|VGAcolumn==8|VGAcolumn==9)) VGAstate=11;  
   else begin 
   if(VGArow==0&VGAcolumn==0) VGAstate=1;
    else 
     if(VGArow==0&VGAcolumn==1) VGAstate=11;
      else VGAstate=12;
  end
 end
 if(Lclc==1) begin
  modenum=1;
  if(Y*(KIcolumn+1)+X>14) OProw=14;
  else
   if(Y*(KIcolumn+1)+X<2) OProw=2;
   else OProw=Y*(KIcolumn+1)+X;
 end
end


if(modenum==1) begin
 KIrow=1;KIcolumn=9;
 if(VGAmodeON==1) begin
  VGAACK=1;
  if(VGArow==1&(VGAcolumn==5|VGAcolumn==6|VGAcolumn==7|VGAcolumn==8|VGAcolumn==9)) VGAstate=11;  
  else begin
   if(VGArow==0&VGAcolumn==1) VGAstate=11;
   else
    if(VGArow==0&VGAcolumn==0) VGAstate=2;
    else VGAstate=12;
  end           
 end
 if(Rclc==1) begin
  modenum=2;
  if(Y*(KIcolumn+1)+X>14) OPcolumn=14;
  else
   if(Y*(KIcolumn+1)+X<2) OPcolumn=2;
   else OPcolumn=Y*(KIcolumn+1)+X;
 end
end

if(modenum==2) begin
 KIrow=15; KIcolumn=15;
 if(VGAmodeON==1) begin
  VGAACK=1;
  if(VGArow==0&VGAcolumn==0) VGAstate=3; else VGAstate=12;
 end
 if(Lclc==1|start==1) begin
  //KIminenum=1;
  Cbuffer[3:0]=X; Cbuffer[7:4]=0; Rbuffer[3:0]=Y; Rbuffer[7:4]=0;    
  buffer[3:0]=KIcolumn; buffer[7:4]=0;
  buffer1[3:0]=OPcolumn; buffer1[7:4]=0;  
  buffer2[3:0]=OProw; buffer2[7:4]=0;
  if(start==0) begin
   start=1;
   buffer3=Rbuffer*(buffer+1)+Cbuffer; buffer4=(buffer1+1)*(buffer2+1)-1;
  end
  else begin
   start=0;  modenum=0; 
   if(buffer3>buffer4) 
    KIminenum=buffer4;
   else 
    KIminenum=buffer3;
 /*if(Rbuffer*(buffer+1)+Cbuffer>(buffer1+1)*(buffer2+1)-1) begin
    KIminenum=(buffer1+1)*(buffer2+1)-1;
   end
   else begin
    KIminenum=(buffer+1)*Rbuffer+Cbuffer;
   end*/
    eokeyin=1;
  end
 end 
end

end


end
endmodule