hardware.v

mining source code written in Verilog

`include "keyinmode.v"
`include "ps2.v"
`include "vga4.v"
`include "randomtest.v"
module hardware(input1,input2,clk,rd,ra/*,light1,light2,light3,light4*/,rbw,rscs,radc,rwe,roe
                ,hor_clk,ver_clk,vlcsp1,vblnp,red,green,blue,rscsV,radcV,raV,rdV,rbwV,rweV,roeV
                ,light
                ,msdata,msclk);

//////////////////////////////////////////////
//////////////////////////////////////////////
//////////////////////////////////////////////
//////////////////////////////////////////////
//////////////////////////////////////////////
input [7:0]input1,input2;
input clk;
/////////////////////////////////////////////
/////////////////////////////////////////////
reg clk5;
reg [1:0]CLKcounter;
always@(posedge clk)
begin
if(CLKcounter==0)
 CLKcounter=1;
else 
 if(CLKcounter==1) begin
   CLKcounter=0;
   if(clk5==0)
    clk5=1;
   else
    clk5=0;
 end
end
//////////////////////////////////////////////
///////////////////////////////////////////
//input [31:0]rd;
inout [31:0]rd;
//input [3:0]X,Y;
//input Lclc,Rclc;
output [15:0]ra;
//output [3:0]light1,light2,light3,light4;
output [3:0]rbw;
output [0:0]rscs,radc,rwe,roe;
//output [3:0]sramin;
//reg [3:0]light1,light2,light3,light4;
reg [3:0]rbw;
reg [0:0]rscs,radc,rwe,roe;
reg [15:0]ra;
reg [3:0]sramin0,datain,sramin1;
reg [19:0]sramin2;
reg writemapst,playst;
reg [3:0]column,row;

////////////////////////
reg [3:0]counter;
reg [7:0]Cbuffer,Rbuffer,CRbuffer;
reg [3:0]buffer,counter2,counter3;
reg [0:0]LUsc,Usc,RUsc,Lsc,Msc,Rsc,LDsc,Dsc,RDsc,writemap,eowritemap,start;
reg [7:0]rabuffer;
reg [2:0]wait1,wait2;


///////////////////////////
//////////////////////////
reg [7:0]columnbuffer,rowbuffer,minecounter,minenum;
reg [7:0]rabuffer2,Xrabuffer1,Yrabuffer1;
//reg [3:0]datain;
reg [0:0]eoplay,win,loss;
reg [7:0]Xbuffer,Ybuffer,bufferA,bufferB;
reg [0:0]Lcbuffer,Rcbuffer,LRcbuffer,Lclc,Rclc;
reg [0:0]write,open,explode,explodeBF,explodeRead,explodeWrite1,explodeWrite4,seperate,SEPscan,SEPwrite,SEPread,flag,unknown,zero,LRbuffer,reset;
reg [2:0]LRmode;
reg modechange;
assign rd=rwe?32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz:{sramin2,datain,sramin1,sramin0};
//sram戈方璶